From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Tsukasa OI <research_trasio@irq.a4lg.com>,
Anup Patel <anup@brainfault.org>,
Heiko Stuebner <heiko@sntech.de>,
Atish Patra <atishp@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>
Subject: [PATCH v6 1/6] RISC-V: Correctly print supported extensions
Date: Mon, 14 Mar 2022 13:38:40 -0700 [thread overview]
Message-ID: <20220314203845.832648-2-atishp@rivosinc.com> (raw)
In-Reply-To: <20220314203845.832648-1-atishp@rivosinc.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
This commit replaces BITS_PER_LONG with number of alphabet letters.
Current ISA pretty-printing code expects extension 'a' (bit 0) through
'z' (bit 25). Although bit 26 and higher is not currently used (thus never
cause an issue in practice), it will be an annoying problem if we start to
use those in the future.
This commit disables printing high bits for now.
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/kernel/cpufeature.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d959d207a40d..dd3d57eb4eea 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -13,6 +13,8 @@
#include <asm/smp.h>
#include <asm/switch_to.h>
+#define NUM_ALPHA_EXTS ('z' - 'a' + 1)
+
unsigned long elf_hwcap __read_mostly;
/* Host ISA bitmap */
@@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void)
{
struct device_node *node;
const char *isa;
- char print_str[BITS_PER_LONG + 1];
+ char print_str[NUM_ALPHA_EXTS + 1];
size_t i, j, isa_len;
static unsigned long isa2hwcap[256] = {0};
@@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void)
}
memset(print_str, 0, sizeof(print_str));
- for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+ for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
if (riscv_isa[0] & BIT_MASK(i))
print_str[j++] = (char)('a' + i);
pr_info("riscv: ISA extensions %s\n", print_str);
memset(print_str, 0, sizeof(print_str));
- for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+ for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
if (elf_hwcap & BIT_MASK(i))
print_str[j++] = (char)('a' + i);
pr_info("riscv: ELF capabilities %s\n", print_str);
--
2.30.2
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next prev parent reply other threads:[~2022-03-14 20:39 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-03-14 20:38 ` Atish Patra [this message]
2022-03-18 3:41 ` [PATCH v6 1/6] RISC-V: Correctly print supported extensions Joe Perches
2022-03-14 20:38 ` [PATCH v6 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
2022-03-15 3:08 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra
2022-03-14 20:38 ` [PATCH v6 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
2022-03-15 3:09 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra
2022-03-15 3:09 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
2022-03-15 3:11 ` Anup Patel
2022-03-18 3:10 ` [PATCH v6 0/6] Provide a fraemework for RISC-V " Palmer Dabbelt
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