From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
Heiko Stuebner <heiko@sntech.de>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>
Subject: [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN
Date: Mon, 14 Mar 2022 13:38:44 -0700 [thread overview]
Message-ID: <20220314203845.832648-6-atishp@rivosinc.com> (raw)
In-Reply-To: <20220314203845.832648-1-atishp@rivosinc.com>
The isa string should begin with either rv64 or rv32. Otherwise, it is
an incorrect isa string. Currently, the string parsing continues even if
it doesnot begin with current XLEN.
Fix this by checking if it found "rv64" or "rv32" in the beginning.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/kernel/cpufeature.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3455fdfd680e..a43c08af5f4b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
for_each_of_cpu_node(node) {
unsigned long this_hwcap = 0;
DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
+ const char *temp;
if (riscv_of_processor_hartid(node) < 0)
continue;
@@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
continue;
}
+ temp = isa;
#if IS_ENABLED(CONFIG_32BIT)
if (!strncmp(isa, "rv32", 4))
isa += 4;
@@ -100,6 +102,9 @@ void __init riscv_fill_hwcap(void)
if (!strncmp(isa, "rv64", 4))
isa += 4;
#endif
+ /* The riscv,isa DT property must start with rv64 or rv32 */
+ if (temp == isa)
+ continue;
bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
for (; *isa; ++isa) {
const char *ext = isa++;
--
2.30.2
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next prev parent reply other threads:[~2022-03-14 20:39 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-03-14 20:38 ` [PATCH v6 1/6] RISC-V: Correctly print supported extensions Atish Patra
2022-03-18 3:41 ` Joe Perches
2022-03-14 20:38 ` [PATCH v6 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
2022-03-15 3:08 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra
2022-03-14 20:38 ` [PATCH v6 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
2022-03-15 3:09 ` Anup Patel
2022-03-14 20:38 ` Atish Patra [this message]
2022-03-15 3:09 ` [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Anup Patel
2022-03-14 20:38 ` [PATCH v6 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
2022-03-15 3:11 ` Anup Patel
2022-03-18 3:10 ` [PATCH v6 0/6] Provide a fraemework for RISC-V " Palmer Dabbelt
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