From: Joe Perches <joe@perches.com>
To: Atish Patra <atishp@rivosinc.com>, linux-kernel@vger.kernel.org
Cc: Tsukasa OI <research_trasio@irq.a4lg.com>,
Anup Patel <anup@brainfault.org>,
Heiko Stuebner <heiko@sntech.de>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH v6 1/6] RISC-V: Correctly print supported extensions
Date: Thu, 17 Mar 2022 20:41:08 -0700 [thread overview]
Message-ID: <4b017a7c75d6422b3e68df1d0aef49adc31ae991.camel@perches.com> (raw)
In-Reply-To: <20220314203845.832648-2-atishp@rivosinc.com>
On Mon, 2022-03-14 at 13:38 -0700, Atish Patra wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> This commit replaces BITS_PER_LONG with number of alphabet letters.
[]
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
[]
> @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void)
> }
>
> memset(print_str, 0, sizeof(print_str));
> - for (i = 0, j = 0; i < BITS_PER_LONG; i++)
> + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
> if (riscv_isa[0] & BIT_MASK(i))
> print_str[j++] = (char)('a' + i);
probably better to add braces for the for loops too
> pr_info("riscv: ISA extensions %s\n", print_str);
>
> memset(print_str, 0, sizeof(print_str));
> - for (i = 0, j = 0; i < BITS_PER_LONG; i++)
> + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
> if (elf_hwcap & BIT_MASK(i))
> print_str[j++] = (char)('a' + i);
> pr_info("riscv: ELF capabilities %s\n", print_str);
and here.
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next prev parent reply other threads:[~2022-03-18 3:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-14 20:38 [PATCH v6 0/6] Provide a fraemework for RISC-V ISA extensions Atish Patra
2022-03-14 20:38 ` [PATCH v6 1/6] RISC-V: Correctly print supported extensions Atish Patra
2022-03-18 3:41 ` Joe Perches [this message]
2022-03-14 20:38 ` [PATCH v6 2/6] RISC-V: Minimal parser for "riscv, isa" strings Atish Patra
2022-03-15 3:08 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 3/6] RISC-V: Extract multi-letter extension names from "riscv, isa" Atish Patra
2022-03-14 20:38 ` [PATCH v6 4/6] RISC-V: Implement multi-letter ISA extension probing framework Atish Patra
2022-03-15 3:09 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 5/6] RISC-V: Do no continue isa string parsing without correct XLEN Atish Patra
2022-03-15 3:09 ` Anup Patel
2022-03-14 20:38 ` [PATCH v6 6/6] RISC-V: Improve /proc/cpuinfo output for ISA extensions Atish Patra
2022-03-15 3:11 ` Anup Patel
2022-03-18 3:10 ` [PATCH v6 0/6] Provide a fraemework for RISC-V " Palmer Dabbelt
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