From: Xu Lu <luxu.kernel@bytedance.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org,
anup@brainfault.org, atishp@atishpatra.org
Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com,
sunjiadong.lff@bytedance.com, xieyongji@bytedance.com,
lihangjing@bytedance.com, chaiwen.cc@bytedance.com,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [RFC 09/12] riscv: Enable NMIs during exceptions
Date: Mon, 23 Oct 2023 16:29:08 +0800 [thread overview]
Message-ID: <20231023082911.23242-10-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com>
We have switched the way of disabling irqs to CSR_IE masking. But
hardware still automatically clearing SIE field of CSR_STATUS whenever
thread traps into kernel, which disabling all irqs including NMIs.
This commit re-enables NMIs and normal irqs during exceptions by setting
the SIE field in CSR_STATUS and restoring NMI and irq bits in CSR_IE.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/include/asm/irqflags.h | 13 +++++++++++++
arch/riscv/include/asm/switch_to.h | 7 +++++++
arch/riscv/kernel/traps.c | 10 ++++++++++
3 files changed, 30 insertions(+)
diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h
index 42f7803582df..6a709e9c69ca 100644
--- a/arch/riscv/include/asm/irqflags.h
+++ b/arch/riscv/include/asm/irqflags.h
@@ -29,6 +29,16 @@ static inline void set_nmi(int irq) {}
static inline void unset_nmi(int irq) {}
+static inline void enable_nmis(void)
+{
+ csr_set(CSR_IE, ALLOWED_NMI_MASK);
+}
+
+static inline void disable_nmis(void)
+{
+ csr_clear(CSR_IE, ALLOWED_NMI_MASK);
+}
+
static inline void local_irq_switch_on(void)
{
csr_set(CSR_STATUS, SR_IE);
@@ -128,6 +138,9 @@ static inline void arch_local_irq_restore(unsigned long flags)
csr_set(CSR_STATUS, flags & SR_IE);
}
+static inline void enable_nmis(void) {}
+static inline void disable_nmis(void) {}
+
#endif /* !CONFIG_RISCV_PSEUDO_NMI */
#endif /* _ASM_RISCV_IRQFLAGS_H */
diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index a727be723c56..116cffeaa6bf 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -84,4 +84,11 @@ do { \
((last) = __switch_to(__prev, __next)); \
} while (0)
+#ifdef CONFIG_RISCV_PSEUDO_NMI
+
+#define prepare_arch_switch(next) disable_nmis()
+#define finish_arch_post_lock_switch() enable_nmis()
+
+#endif /* CONFIG_RISCV_PSEUDO_NMI */
+
#endif /* _ASM_RISCV_SWITCH_TO_H */
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index fae8f610d867..63d3c1417563 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -135,7 +135,9 @@ asmlinkage __visible __trap_section void name(struct pt_regs *regs) \
{ \
if (user_mode(regs)) { \
irqentry_enter_from_user_mode(regs); \
+ enable_nmis(); \
do_trap_error(regs, signo, code, regs->epc, "Oops - " str); \
+ disable_nmis(); \
irqentry_exit_to_user_mode(regs); \
} else { \
irqentry_state_t state = irqentry_nmi_enter(regs); \
@@ -292,8 +294,12 @@ asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs)
if (user_mode(regs)) {
irqentry_enter_from_user_mode(regs);
+ enable_nmis();
+
handle_break(regs);
+ disable_nmis();
+
irqentry_exit_to_user_mode(regs);
} else {
irqentry_state_t state = irqentry_nmi_enter(regs);
@@ -338,10 +344,14 @@ asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs)
{
irqentry_state_t state = irqentry_enter(regs);
+ enable_nmis();
+
handle_page_fault(regs);
local_irq_disable();
+ disable_nmis();
+
irqentry_exit(regs, state);
}
#endif
--
2.20.1
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next prev parent reply other threads:[~2023-10-23 8:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 8:28 [RFC 00/12] riscv: Introduce Pseudo NMI Xu Lu
2023-10-23 8:29 ` [RFC 01/12] riscv: Introduce CONFIG_RISCV_PSEUDO_NMI Xu Lu
2023-10-23 8:29 ` [RFC 02/12] riscv: Make CSR_IE register part of context Xu Lu
2023-10-23 8:29 ` [RFC 03/12] riscv: Switch to CSR_IE masking when disabling irqs Xu Lu
2023-10-23 8:29 ` [RFC 04/12] riscv: Switch back to CSR_STATUS masking when going idle Xu Lu
2023-10-23 8:29 ` [RFC 05/12] riscv: kvm: Switch back to CSR_STATUS masking when entering guest Xu Lu
2023-10-23 8:29 ` [RFC 06/12] riscv: Allow requesting irq as pseudo NMI Xu Lu
2023-10-23 8:29 ` [RFC 07/12] riscv: Handle pseudo NMI in arch irq handler Xu Lu
2023-10-23 8:29 ` [RFC 08/12] riscv: Enable NMIs during irqs disabled context Xu Lu
2023-10-23 8:29 ` Xu Lu [this message]
2023-10-23 8:29 ` [RFC 10/12] riscv: Enable NMIs during interrupt handling Xu Lu
2023-10-23 8:29 ` [RFC 11/12] riscv: Request pmu overflow interrupt as NMI Xu Lu
2023-10-23 8:29 ` [RFC 12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default Xu Lu
2023-10-25 23:01 ` [RFC 00/12] riscv: Introduce Pseudo NMI Atish Patra
2023-10-26 13:56 ` [External] " Xu Lu
2023-10-26 19:41 ` Atish Patra
2023-10-27 7:33 ` Xu Lu
2023-10-27 7:55 ` Thomas Gleixner
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