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From: Xu Lu <luxu.kernel@bytedance.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org,
	anup@brainfault.org, atishp@atishpatra.org
Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com,
	sunjiadong.lff@bytedance.com, xieyongji@bytedance.com,
	lihangjing@bytedance.com, chaiwen.cc@bytedance.com,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	Xu Lu <luxu.kernel@bytedance.com>
Subject: [RFC 04/12] riscv: Switch back to CSR_STATUS masking when going idle
Date: Mon, 23 Oct 2023 16:29:03 +0800	[thread overview]
Message-ID: <20231023082911.23242-5-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com>

The WFI instruction makes current core stall until interrupt happens.
In WFI's implementation, core can only be waken up from interrupt
which is both pending in CSR_IP and enabled in CSR_IE. After we switch
to CSR_IE masking for irq disabling, WFI instruction can never resume
execution if CSR_IE is masked.

This commit handles this special case. When WFI instruction is called with
CSR_IE masked, we unmask CSR_IE first and disable irqs in traditional
CSR_STATUS way instead.

Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
 arch/riscv/include/asm/processor.h |  4 ++++
 arch/riscv/kernel/irq.c            | 17 +++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 3e23e1786d05..ab9b2b974979 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -111,10 +111,14 @@ extern void start_thread(struct pt_regs *regs,
 extern unsigned long __get_wchan(struct task_struct *p);
 
 
+#ifndef CONFIG_RISCV_PSEUDO_NMI
 static inline void wait_for_interrupt(void)
 {
 	__asm__ __volatile__ ("wfi");
 }
+#else
+void wait_for_interrupt(void);
+#endif
 
 struct device_node;
 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index 9cc0a7669271..e7dfd68e9ca3 100644
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@ -15,6 +15,23 @@
 #include <asm/softirq_stack.h>
 #include <asm/stacktrace.h>
 
+#ifdef CONFIG_RISCV_PSEUDO_NMI
+
+void wait_for_interrupt(void)
+{
+	if (irqs_disabled()) {
+		local_irq_switch_off();
+		local_irq_enable();
+		__asm__ __volatile__ ("wfi");
+		local_irq_disable();
+		local_irq_switch_on();
+	} else {
+		__asm__ __volatile__ ("wfi");
+	}
+}
+
+#endif /* CONFIG_RISCV_PSEUDO_NMI */
+
 static struct fwnode_handle *(*__get_intc_node)(void);
 
 void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void))
-- 
2.20.1


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  parent reply	other threads:[~2023-10-23  8:29 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23  8:28 [RFC 00/12] riscv: Introduce Pseudo NMI Xu Lu
2023-10-23  8:29 ` [RFC 01/12] riscv: Introduce CONFIG_RISCV_PSEUDO_NMI Xu Lu
2023-10-23  8:29 ` [RFC 02/12] riscv: Make CSR_IE register part of context Xu Lu
2023-10-23  8:29 ` [RFC 03/12] riscv: Switch to CSR_IE masking when disabling irqs Xu Lu
2023-10-23  8:29 ` Xu Lu [this message]
2023-10-23  8:29 ` [RFC 05/12] riscv: kvm: Switch back to CSR_STATUS masking when entering guest Xu Lu
2023-10-23  8:29 ` [RFC 06/12] riscv: Allow requesting irq as pseudo NMI Xu Lu
2023-10-23  8:29 ` [RFC 07/12] riscv: Handle pseudo NMI in arch irq handler Xu Lu
2023-10-23  8:29 ` [RFC 08/12] riscv: Enable NMIs during irqs disabled context Xu Lu
2023-10-23  8:29 ` [RFC 09/12] riscv: Enable NMIs during exceptions Xu Lu
2023-10-23  8:29 ` [RFC 10/12] riscv: Enable NMIs during interrupt handling Xu Lu
2023-10-23  8:29 ` [RFC 11/12] riscv: Request pmu overflow interrupt as NMI Xu Lu
2023-10-23  8:29 ` [RFC 12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default Xu Lu
2023-10-25 23:01 ` [RFC 00/12] riscv: Introduce Pseudo NMI Atish Patra
2023-10-26 13:56   ` [External] " Xu Lu
2023-10-26 19:41     ` Atish Patra
2023-10-27  7:33       ` Xu Lu
2023-10-27  7:55     ` Thomas Gleixner

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