From: Xu Lu <luxu.kernel@bytedance.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org,
anup@brainfault.org, atishp@atishpatra.org
Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com,
sunjiadong.lff@bytedance.com, xieyongji@bytedance.com,
lihangjing@bytedance.com, chaiwen.cc@bytedance.com,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [RFC 11/12] riscv: Request pmu overflow interrupt as NMI
Date: Mon, 23 Oct 2023 16:29:10 +0800 [thread overview]
Message-ID: <20231023082911.23242-12-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com>
This commit registers pmu overflow interrupt as NMI to improve the accuracy
of perf sampling.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/include/asm/irqflags.h | 2 +-
drivers/perf/riscv_pmu_sbi.c | 23 +++++++++++++++++++----
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h
index 6a709e9c69ca..be840e297559 100644
--- a/arch/riscv/include/asm/irqflags.h
+++ b/arch/riscv/include/asm/irqflags.h
@@ -12,7 +12,7 @@
#ifdef CONFIG_RISCV_PSEUDO_NMI
-#define __ALLOWED_NMI_MASK 0
+#define __ALLOWED_NMI_MASK BIT(IRQ_PMU_OVF)
#define ALLOWED_NMI_MASK (__ALLOWED_NMI_MASK & irqs_enabled_ie)
static inline bool nmi_allowed(int irq)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 995b501ec721..85abb7dd43b9 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -760,6 +760,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
{
+ int ret = 0;
struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
@@ -778,20 +779,30 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
if (riscv_pmu_use_irq) {
cpu_hw_evt->irq = riscv_pmu_irq;
csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
-#ifndef CONFIG_RISCV_PSEUDO_NMI
+#ifdef CONFIG_RISCV_PSEUDO_NMI
+ ret = prepare_percpu_nmi(riscv_pmu_irq);
+ if (ret != 0) {
+ pr_err("Failed to prepare percpu nmi:%d\n", ret);
+ return ret;
+ }
+ enable_percpu_nmi(riscv_pmu_irq, IRQ_TYPE_NONE);
+#else
csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
-#endif
enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
+#endif
}
- return 0;
+ return ret;
}
static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
{
if (riscv_pmu_use_irq) {
+#ifdef CONFIG_RISCV_PSEUDO_NMI
+ disable_percpu_nmi(riscv_pmu_irq);
+ teardown_percpu_nmi(riscv_pmu_irq);
+#else
disable_percpu_irq(riscv_pmu_irq);
-#ifndef CONFIG_RISCV_PSEUDO_NMI
csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
#endif
}
@@ -835,7 +846,11 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
return -ENODEV;
}
+#ifdef CONFIG_RISCV_PSEUDO_NMI
+ ret = request_percpu_nmi(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events);
+#else
ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events);
+#endif
if (ret) {
pr_err("registering percpu irq failed [%d]\n", ret);
return ret;
--
2.20.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-10-23 8:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 8:28 [RFC 00/12] riscv: Introduce Pseudo NMI Xu Lu
2023-10-23 8:29 ` [RFC 01/12] riscv: Introduce CONFIG_RISCV_PSEUDO_NMI Xu Lu
2023-10-23 8:29 ` [RFC 02/12] riscv: Make CSR_IE register part of context Xu Lu
2023-10-23 8:29 ` [RFC 03/12] riscv: Switch to CSR_IE masking when disabling irqs Xu Lu
2023-10-23 8:29 ` [RFC 04/12] riscv: Switch back to CSR_STATUS masking when going idle Xu Lu
2023-10-23 8:29 ` [RFC 05/12] riscv: kvm: Switch back to CSR_STATUS masking when entering guest Xu Lu
2023-10-23 8:29 ` [RFC 06/12] riscv: Allow requesting irq as pseudo NMI Xu Lu
2023-10-23 8:29 ` [RFC 07/12] riscv: Handle pseudo NMI in arch irq handler Xu Lu
2023-10-23 8:29 ` [RFC 08/12] riscv: Enable NMIs during irqs disabled context Xu Lu
2023-10-23 8:29 ` [RFC 09/12] riscv: Enable NMIs during exceptions Xu Lu
2023-10-23 8:29 ` [RFC 10/12] riscv: Enable NMIs during interrupt handling Xu Lu
2023-10-23 8:29 ` Xu Lu [this message]
2023-10-23 8:29 ` [RFC 12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default Xu Lu
2023-10-25 23:01 ` [RFC 00/12] riscv: Introduce Pseudo NMI Atish Patra
2023-10-26 13:56 ` [External] " Xu Lu
2023-10-26 19:41 ` Atish Patra
2023-10-27 7:33 ` Xu Lu
2023-10-27 7:55 ` Thomas Gleixner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231023082911.23242-12-luxu.kernel@bytedance.com \
--to=luxu.kernel@bytedance.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@atishpatra.org \
--cc=chaiwen.cc@bytedance.com \
--cc=dengliang.1214@bytedance.com \
--cc=lihangjing@bytedance.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=liyu.yukiteru@bytedance.com \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=sunjiadong.lff@bytedance.com \
--cc=tglx@linutronix.de \
--cc=xieyongji@bytedance.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox