From: Xu Lu <luxu.kernel@bytedance.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org,
anup@brainfault.org, atishp@atishpatra.org
Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com,
sunjiadong.lff@bytedance.com, xieyongji@bytedance.com,
lihangjing@bytedance.com, chaiwen.cc@bytedance.com,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [RFC 10/12] riscv: Enable NMIs during interrupt handling
Date: Mon, 23 Oct 2023 16:29:09 +0800 [thread overview]
Message-ID: <20231023082911.23242-11-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com>
Hardware automatically clearing SIE field of CSR_STATUS whenever
thread traps into kernel by interrupt, disabling all irqs including NMIs
during interrupt handling.
This commit re-enable NMIs during interrupt handling by setting the SIE
field in CSR_STATUS and restoring NMIs bits in CSR_IE. Normal interrupts
are still disabled during interrupt handling and NMIs are also disabled
during NMIs handling to avoid nesting.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
Signed-off-by: Hangjing Li <lihangjing@bytedance.com>
Reviewed-by: Liang Deng <dengliang.1214@bytedance.com>
Reviewed-by: Yu Li <liyu.yukiteru@bytedance.com>
---
arch/riscv/kernel/traps.c | 44 +++++++++++++++++++++++---------
drivers/irqchip/irq-riscv-intc.c | 2 ++
2 files changed, 34 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 63d3c1417563..185743edfa09 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -356,20 +356,11 @@ asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs)
}
#endif
-static void noinstr handle_riscv_irq(struct pt_regs *regs)
+static void noinstr do_interrupt(struct pt_regs *regs)
{
struct pt_regs *old_regs;
- irq_enter_rcu();
old_regs = set_irq_regs(regs);
- handle_arch_irq(regs);
- set_irq_regs(old_regs);
- irq_exit_rcu();
-}
-
-asmlinkage void noinstr do_irq(struct pt_regs *regs)
-{
- irqentry_state_t state = irqentry_enter(regs);
#ifdef CONFIG_IRQ_STACKS
if (on_thread_stack()) {
ulong *sp = per_cpu(irq_stack_ptr, smp_processor_id())
@@ -382,7 +373,9 @@ asmlinkage void noinstr do_irq(struct pt_regs *regs)
"addi s0, sp, 2*"RISCV_SZPTR "\n"
"move sp, %[sp] \n"
"move a0, %[regs] \n"
- "call handle_riscv_irq \n"
+ "la t0, handle_arch_irq \n"
+ REG_L" t1, (t0) \n"
+ "jalr t1 \n"
"addi sp, s0, -2*"RISCV_SZPTR"\n"
REG_L" s0, (sp) \n"
"addi sp, sp, "RISCV_SZPTR "\n"
@@ -398,11 +391,38 @@ asmlinkage void noinstr do_irq(struct pt_regs *regs)
"memory");
} else
#endif
- handle_riscv_irq(regs);
+ handle_arch_irq(regs);
+ set_irq_regs(old_regs);
+}
+
+static __always_inline void __do_nmi(struct pt_regs *regs)
+{
+ irqentry_state_t state = irqentry_nmi_enter(regs);
+
+ do_interrupt(regs);
+
+ irqentry_nmi_exit(regs, state);
+}
+
+static __always_inline void __do_irq(struct pt_regs *regs)
+{
+ irqentry_state_t state = irqentry_enter(regs);
+
+ irq_enter_rcu();
+ do_interrupt(regs);
+ irq_exit_rcu();
irqentry_exit(regs, state);
}
+asmlinkage void noinstr do_irq(struct pt_regs *regs)
+{
+ if (IS_ENABLED(CONFIG_RISCV_PSEUDO_NMI) && regs_irqs_disabled(regs))
+ __do_nmi(regs);
+ else
+ __do_irq(regs);
+}
+
#ifdef CONFIG_GENERIC_BUG
int is_valid_bugaddr(unsigned long pc)
{
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index c672c0c64d5d..80ed8606e04d 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -34,7 +34,9 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
generic_handle_domain_nmi(intc_domain, cause);
nmi_exit();
} else {
+ enable_nmis();
generic_handle_domain_irq(intc_domain, cause);
+ disable_nmis();
}
}
--
2.20.1
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next prev parent reply other threads:[~2023-10-23 8:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 8:28 [RFC 00/12] riscv: Introduce Pseudo NMI Xu Lu
2023-10-23 8:29 ` [RFC 01/12] riscv: Introduce CONFIG_RISCV_PSEUDO_NMI Xu Lu
2023-10-23 8:29 ` [RFC 02/12] riscv: Make CSR_IE register part of context Xu Lu
2023-10-23 8:29 ` [RFC 03/12] riscv: Switch to CSR_IE masking when disabling irqs Xu Lu
2023-10-23 8:29 ` [RFC 04/12] riscv: Switch back to CSR_STATUS masking when going idle Xu Lu
2023-10-23 8:29 ` [RFC 05/12] riscv: kvm: Switch back to CSR_STATUS masking when entering guest Xu Lu
2023-10-23 8:29 ` [RFC 06/12] riscv: Allow requesting irq as pseudo NMI Xu Lu
2023-10-23 8:29 ` [RFC 07/12] riscv: Handle pseudo NMI in arch irq handler Xu Lu
2023-10-23 8:29 ` [RFC 08/12] riscv: Enable NMIs during irqs disabled context Xu Lu
2023-10-23 8:29 ` [RFC 09/12] riscv: Enable NMIs during exceptions Xu Lu
2023-10-23 8:29 ` Xu Lu [this message]
2023-10-23 8:29 ` [RFC 11/12] riscv: Request pmu overflow interrupt as NMI Xu Lu
2023-10-23 8:29 ` [RFC 12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default Xu Lu
2023-10-25 23:01 ` [RFC 00/12] riscv: Introduce Pseudo NMI Atish Patra
2023-10-26 13:56 ` [External] " Xu Lu
2023-10-26 19:41 ` Atish Patra
2023-10-27 7:33 ` Xu Lu
2023-10-27 7:55 ` Thomas Gleixner
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