* [PATCH 01/11] riscv: dts: sophgo: sg2044: Add system controller device
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 02/11] riscv: dts: sophgo: sg2044: Add clock " Inochi Amaoto
` (10 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
The TOP system controller device is necessary for the SG2044 clock
controller. Add it to the SoC device tree.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index d67e45f77d6e..a0c13d8d26af 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -76,6 +76,13 @@ uart3: serial@7030003000 {
status = "disabled";
};
+ syscon: syscon@7050000000 {
+ compatible = "sophgo,sg2044-top-syscon", "syscon";
+ reg = <0x70 0x50000000 0x0 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ };
+
rst: reset-controller@7050003000 {
compatible = "sophgo,sg2044-reset",
"sophgo,sg2042-reset";
--
2.49.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 02/11] riscv: dts: sophgo: sg2044: Add clock controller device
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
2025-06-08 23:28 ` [PATCH 01/11] riscv: dts: sophgo: sg2044: Add system controller device Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 03/11] riscv: dts: sophgo: sg2044: Add GPIO device Inochi Amaoto
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
Add clock controller and pll clock node for sg2044.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 34 ++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index a0c13d8d26af..d21a59948186 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
*/
+#include <dt-bindings/clock/sophgo,sg2044-pll.h>
+#include <dt-bindings/clock/sophgo,sg2044-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "sg2044-cpus.dtsi"
@@ -32,6 +34,9 @@ uart0: serial@7030000000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30000000 0x0 0x1000>;
clock-frequency = <500000000>;
+ clocks = <&clk CLK_GATE_UART_500M>,
+ <&clk CLK_GATE_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
interrupt-parent = <&intc>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -44,6 +49,9 @@ uart1: serial@7030001000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30001000 0x0 0x1000>;
clock-frequency = <500000000>;
+ clocks = <&clk CLK_GATE_UART_500M>,
+ <&clk CLK_GATE_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
interrupt-parent = <&intc>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -56,6 +64,9 @@ uart2: serial@7030002000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30002000 0x0 0x1000>;
clock-frequency = <500000000>;
+ clocks = <&clk CLK_GATE_UART_500M>,
+ <&clk CLK_GATE_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
interrupt-parent = <&intc>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -68,6 +79,9 @@ uart3: serial@7030003000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30003000 0x0 0x1000>;
clock-frequency = <500000000>;
+ clocks = <&clk CLK_GATE_UART_500M>,
+ <&clk CLK_GATE_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
interrupt-parent = <&intc>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -83,6 +97,26 @@ syscon: syscon@7050000000 {
clocks = <&osc>;
};
+ clk: clock-controller@7050002000 {
+ compatible = "sophgo,sg2044-clk";
+ reg = <0x70 0x50002000 0x0 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
+ <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
+ <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
+ <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
+ <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
+ <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
+ <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
+ <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
+ <&syscon CLK_MPLL5>;
+ clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
+ "dpll1", "dpll2", "dpll3", "dpll4",
+ "dpll5", "dpll6", "dpll7", "mpll0",
+ "mpll1", "mpll2", "mpll3", "mpll4",
+ "mpll5";
+ };
+
rst: reset-controller@7050003000 {
compatible = "sophgo,sg2044-reset",
"sophgo,sg2042-reset";
--
2.49.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 03/11] riscv: dts: sophgo: sg2044: Add GPIO device
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
2025-06-08 23:28 ` [PATCH 01/11] riscv: dts: sophgo: sg2044: Add system controller device Inochi Amaoto
2025-06-08 23:28 ` [PATCH 02/11] riscv: dts: sophgo: sg2044: Add clock " Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 04/11] riscv: dts: sophgo: sg2044: Add I2C device Inochi Amaoto
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
The GPIO controller is a standard Synopsys IP, which is already
supported by the kernel.
Add GPIO DT node for SG2044 SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 70 ++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index d21a59948186..70d1096f959f 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/sophgo,sg2044-pll.h>
#include <dt-bindings/clock/sophgo,sg2044-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
#include "sg2044-cpus.dtsi"
#include "sg2044-reset.h"
@@ -90,6 +91,75 @@ uart3: serial@7030003000 {
status = "disabled";
};
+ gpio0: gpio@7040009000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x70 0x40009000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_GATE_APB_GPIO>,
+ <&clk CLK_GATE_GPIO_DB>;
+ clock-names = "bus", "db";
+ resets = <&rst RST_GPIO0>;
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio1: gpio@704000a000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x70 0x4000a000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_GATE_APB_GPIO>,
+ <&clk CLK_GATE_GPIO_DB>;
+ clock-names = "bus", "db";
+ resets = <&rst RST_GPIO1>;
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio2: gpio@704000b000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x70 0x4000b000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_GATE_APB_GPIO>,
+ <&clk CLK_GATE_GPIO_DB>;
+ clock-names = "bus", "db";
+ resets = <&rst RST_GPIO2>;
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
syscon: syscon@7050000000 {
compatible = "sophgo,sg2044-top-syscon", "syscon";
reg = <0x70 0x50000000 0x0 0x1000>;
--
2.49.0
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 04/11] riscv: dts: sophgo: sg2044: Add I2C device
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
` (2 preceding siblings ...)
2025-06-08 23:28 ` [PATCH 03/11] riscv: dts: sophgo: sg2044: Add GPIO device Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 05/11] riscv: dts: sophgo: sg2044: add DMA controller device Inochi Amaoto
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
The I2C controller of SG2044 is a standard Synopsys IP, with one
the ref clock is need.
Add I2C DT node for SG2044 SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 56 ++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index 70d1096f959f..a25cbb78913d 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -91,6 +91,62 @@ uart3: serial@7030003000 {
status = "disabled";
};
+ i2c0: i2c@7040005000 {
+ compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
+ reg = <0x70 0x40005000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ clocks = <&clk CLK_GATE_APB_I2C>;
+ clock-names = "ref";
+ interrupt-parent = <&intc>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@7040006000 {
+ compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
+ reg = <0x70 0x40006000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ clocks = <&clk CLK_GATE_APB_I2C>;
+ clock-names = "ref";
+ interrupt-parent = <&intc>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@7040007000 {
+ compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
+ reg = <0x70 0x40007000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ clocks = <&clk CLK_GATE_APB_I2C>;
+ clock-names = "ref";
+ interrupt-parent = <&intc>;
+ interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@7040008000 {
+ compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
+ reg = <0x70 0x40008000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ clocks = <&clk CLK_GATE_APB_I2C>;
+ clock-names = "ref";
+ interrupt-parent = <&intc>;
+ interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C3>;
+ status = "disabled";
+ };
+
gpio0: gpio@7040009000 {
compatible = "snps,dw-apb-gpio";
reg = <0x70 0x40009000 0x0 0x1000>;
--
2.49.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 05/11] riscv: dts: sophgo: sg2044: add DMA controller device
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
` (3 preceding siblings ...)
2025-06-08 23:28 ` [PATCH 04/11] riscv: dts: sophgo: sg2044: Add I2C device Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 06/11] riscv: dts: sophgo: sg2044: Add MMC " Inochi Amaoto
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
The DMA controller of SG2044 is a standard Synopsys IP, which is
already supported by the kernel.
Add DMA controller DT node for SG2044.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index a25cbb78913d..a4d2f8a13cc3 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -31,6 +31,26 @@ soc {
#size-cells = <2>;
ranges;
+ dmac0: dma-controller@7020000000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x70 0x20000000 0x0 0x10000>;
+ #dma-cells = <1>;
+ clock-names = "core-clk", "cfgr-clk";
+ clocks = <&clk CLK_GATE_SYSDMA_AXI>,
+ <&clk CLK_GATE_SYSDMA_AXI>;
+ dma-noncoherent;
+ interrupt-parent = <&intc>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <8>;
+ snps,priority = <0 1 2 3 4 5 6 7>;
+ snps,block-size = <4096 4096 4096 4096
+ 4096 4096 4096 4096>;
+ snps,dma-masters = <2>;
+ snps,data-width = <2>;
+ snps,axi-max-burst-len = <4>;
+ status = "disabled";
+ };
+
uart0: serial@7030000000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30000000 0x0 0x1000>;
--
2.49.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 06/11] riscv: dts: sophgo: sg2044: Add MMC controller device
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
` (4 preceding siblings ...)
2025-06-08 23:28 ` [PATCH 05/11] riscv: dts: sophgo: sg2044: add DMA controller device Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 07/11] riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device Inochi Amaoto
` (5 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, linux-kernel, netdev, Yixun Lan
Add emmc controller and sd controller DT node for SG2044.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
.../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 17 +++++++++++++
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 24 +++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
index 54cdf4239d5f..d077923097e8 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
@@ -27,6 +27,23 @@ &osc {
clock-frequency = <25000000>;
};
+&emmc {
+ bus-width = <4>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ wp-inverted;
+ status = "okay";
+};
+
+&sd {
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ wp-inverted;
+ status = "okay";
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index a4d2f8a13cc3..6067901cde1e 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -111,6 +111,30 @@ uart3: serial@7030003000 {
status = "disabled";
};
+ emmc: mmc@703000a000 {
+ compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
+ reg = <0x70 0x3000a000 0x0 0x1000>;
+ clocks = <&clk CLK_GATE_EMMC>,
+ <&clk CLK_GATE_AXI_EMMC>,
+ <&clk CLK_GATE_EMMC_100K>;
+ clock-names = "core", "bus", "timer";
+ interrupt-parent = <&intc>;
+ interrupts = <298 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sd: mmc@703000b000 {
+ compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
+ reg = <0x70 0x3000b000 0x0 0x1000>;
+ clocks = <&clk CLK_GATE_SD>,
+ <&clk CLK_GATE_AXI_SD>,
+ <&clk CLK_GATE_SD_100K>;
+ clock-names = "core", "bus", "timer";
+ interrupt-parent = <&intc>;
+ interrupts = <300 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c0: i2c@7040005000 {
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
reg = <0x70 0x40005000 0x0 0x1000>;
--
2.49.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 07/11] riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
` (5 preceding siblings ...)
2025-06-08 23:28 ` [PATCH 06/11] riscv: dts: sophgo: sg2044: Add MMC " Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 08/11] riscv: dts: sophgo: sg2044: Add ethernet control device Inochi Amaoto
` (4 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
Add MCU devicetree node for Sophgo SRD3-10 board. This is used to
provide SUSP function for the board.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
index d077923097e8..75564b2719cd 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
@@ -36,6 +36,16 @@ &emmc {
status = "okay";
};
+&i2c1 {
+ status = "okay";
+
+ mcu: syscon@17 {
+ compatible = "sophgo,sg2044-hwmon-mcu", "sophgo,sg2042-hwmon-mcu";
+ reg = <0x17>;
+ #thermal-sensor-cells = <1>;
+ };
+};
+
&sd {
bus-width = <4>;
no-sdio;
--
2.49.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 08/11] riscv: dts: sophgo: sg2044: Add ethernet control device
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
` (6 preceding siblings ...)
2025-06-08 23:28 ` [PATCH 07/11] riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 09/11] riscv: dts: sophgo: sg2044: Add pinctrl device Inochi Amaoto
` (3 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
Add ethernet control node for sg2044.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
.../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 17 +++++
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 62 +++++++++++++++++++
2 files changed, 79 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
index 75564b2719cd..01340f21848f 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
@@ -36,6 +36,23 @@ &emmc {
status = "okay";
};
+&gmac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ phy0: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&porta 28 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ rx-internal-delay-ps = <2050>;
+ };
+ };
+};
+
&i2c1 {
status = "okay";
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index 6067901cde1e..bbf4191fb87d 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -111,6 +111,68 @@ uart3: serial@7030003000 {
status = "disabled";
};
+ gmac0: ethernet@7030006000 {
+ compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a";
+ reg = <0x70 0x30006000 0x0 0x4000>;
+ clocks = <&clk CLK_GATE_AXI_ETH0>,
+ <&clk CLK_GATE_PTP_REF_I_ETH0>,
+ <&clk CLK_GATE_TX_ETH0>;
+ clock-names = "stmmaceth", "ptp_ref", "tx";
+ dma-noncoherent;
+ interrupt-parent = <&intc>;
+ interrupts = <296 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&rst RST_ETH0>;
+ reset-names = "stmmaceth";
+ snps,multicast-filter-bins = <0>;
+ snps,perfect-filter-entries = <1>;
+ snps,aal;
+ snps,tso;
+ snps,txpbl = <32>;
+ snps,rxpbl = <32>;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ status = "disabled";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-wsp;
+ queue0 {};
+ queue1 {};
+ queue2 {};
+ queue3 {};
+ queue4 {};
+ queue5 {};
+ queue6 {};
+ queue7 {};
+ };
+
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+ queue0 {};
+ queue1 {};
+ queue2 {};
+ queue3 {};
+ queue4 {};
+ queue5 {};
+ queue6 {};
+ queue7 {};
+ };
+
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <16 8 4 0 0 0 0>;
+ snps,wr_osr_lmt = <1>;
+ snps,rd_osr_lmt = <2>;
+ };
+ };
+
emmc: mmc@703000a000 {
compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
reg = <0x70 0x3000a000 0x0 0x1000>;
--
2.49.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 09/11] riscv: dts: sophgo: sg2044: Add pinctrl device
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
` (7 preceding siblings ...)
2025-06-08 23:28 ` [PATCH 08/11] riscv: dts: sophgo: sg2044: Add ethernet control device Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 10/11] riscv: dts: sophgo: add SG2044 SPI NOR controller driver Inochi Amaoto
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
Add pinctrl DT node and configuration for SG2044.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index bbf4191fb87d..be20efd8e2ac 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/sophgo,sg2044-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-sg2044.h>
#include "sg2044-cpus.dtsi"
#include "sg2044-reset.h"
@@ -329,6 +330,11 @@ syscon: syscon@7050000000 {
clocks = <&osc>;
};
+ pinctrl: pinctrl@7050001000 {
+ compatible = "sophgo,sg2044-pinctrl";
+ reg = <0x70 0x50001000 0x0 0x1000>;
+ };
+
clk: clock-controller@7050002000 {
compatible = "sophgo,sg2044-clk";
reg = <0x70 0x50002000 0x0 0x1000>;
--
2.49.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 10/11] riscv: dts: sophgo: add SG2044 SPI NOR controller driver
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
` (8 preceding siblings ...)
2025-06-08 23:28 ` [PATCH 09/11] riscv: dts: sophgo: sg2044: Add pinctrl device Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-08 23:28 ` [PATCH 11/11] riscv: dts: sophgo: add pwm controller for SG2044 Inochi Amaoto
2025-06-17 5:07 ` [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
From: Longbin Li <looong.bin@gmail.com>
Add SPI NOR device node for SG2044.
Signed-off-by: Longbin Li <looong.bin@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index be20efd8e2ac..b65e491deb8f 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -32,6 +32,30 @@ soc {
#size-cells = <2>;
ranges;
+ spifmc0: spi@7001000000 {
+ compatible = "sophgo,sg2044-spifmc-nor";
+ reg = <0x70 0x01000000 0x0 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_GATE_AHB_SPIFMC>;
+ interrupt-parent = <&intc>;
+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPIFMC0>;
+ status = "disabled";
+ };
+
+ spifmc1: spi@7005000000 {
+ compatible = "sophgo,sg2044-spifmc-nor";
+ reg = <0x70 0x05000000 0x0 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk CLK_GATE_AHB_SPIFMC>;
+ interrupt-parent = <&intc>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPIFMC1>;
+ status = "disabled";
+ };
+
dmac0: dma-controller@7020000000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x70 0x20000000 0x0 0x10000>;
--
2.49.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 11/11] riscv: dts: sophgo: add pwm controller for SG2044
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
` (9 preceding siblings ...)
2025-06-08 23:28 ` [PATCH 10/11] riscv: dts: sophgo: add SG2044 SPI NOR controller driver Inochi Amaoto
@ 2025-06-08 23:28 ` Inochi Amaoto
2025-06-11 9:53 ` Chen Wang
2025-06-17 5:07 ` [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
11 siblings, 1 reply; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-08 23:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
From: Longbin Li <looong.bin@gmail.com>
Add pwm device node for SG2044.
Signed-off-by: Longbin Li <looong.bin@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 10 ++++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
index 01340f21848f..b50c3a872d8b 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
@@ -63,6 +63,10 @@ mcu: syscon@17 {
};
};
+&pwm {
+ status = "okay";
+};
+
&sd {
bus-width = <4>;
no-sdio;
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index b65e491deb8f..f88cabe75790 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -347,6 +347,16 @@ portc: gpio-controller@0 {
};
};
+ pwm: pwm@704000c000 {
+ compatible = "sophgo,sg2044-pwm";
+ reg = <0x70 0x4000c000 0x0 0x1000>;
+ #pwm-cells = <3>;
+ clocks = <&clk CLK_GATE_APB_PWM>;
+ clock-names = "apb";
+ resets = <&rst RST_PWM>;
+ status = "disabled";
+ };
+
syscon: syscon@7050000000 {
compatible = "sophgo,sg2044-top-syscon", "syscon";
reg = <0x70 0x50000000 0x0 0x1000>;
--
2.49.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 11/11] riscv: dts: sophgo: add pwm controller for SG2044
2025-06-08 23:28 ` [PATCH 11/11] riscv: dts: sophgo: add pwm controller for SG2044 Inochi Amaoto
@ 2025-06-11 9:53 ` Chen Wang
2025-06-11 10:17 ` Inochi Amaoto
0 siblings, 1 reply; 15+ messages in thread
From: Chen Wang @ 2025-06-11 9:53 UTC (permalink / raw)
To: Inochi Amaoto, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
"sophgo,sg2044-pwm" should have not been in 6.16, submit this after that?
Others. LGTM.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Thanks
On 2025/6/9 7:28, Inochi Amaoto wrote:
> From: Longbin Li <looong.bin@gmail.com>
>
> Add pwm device node for SG2044.
>
> Signed-off-by: Longbin Li <looong.bin@gmail.com>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++
> arch/riscv/boot/dts/sophgo/sg2044.dtsi | 10 ++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
> index 01340f21848f..b50c3a872d8b 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
> +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
> @@ -63,6 +63,10 @@ mcu: syscon@17 {
> };
> };
>
> +&pwm {
> + status = "okay";
> +};
> +
> &sd {
> bus-width = <4>;
> no-sdio;
> diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
> index b65e491deb8f..f88cabe75790 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
> @@ -347,6 +347,16 @@ portc: gpio-controller@0 {
> };
> };
>
> + pwm: pwm@704000c000 {
> + compatible = "sophgo,sg2044-pwm";
> + reg = <0x70 0x4000c000 0x0 0x1000>;
> + #pwm-cells = <3>;
> + clocks = <&clk CLK_GATE_APB_PWM>;
> + clock-names = "apb";
> + resets = <&rst RST_PWM>;
> + status = "disabled";
> + };
> +
> syscon: syscon@7050000000 {
> compatible = "sophgo,sg2044-top-syscon", "syscon";
> reg = <0x70 0x50000000 0x0 0x1000>;
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 11/11] riscv: dts: sophgo: add pwm controller for SG2044
2025-06-11 9:53 ` Chen Wang
@ 2025-06-11 10:17 ` Inochi Amaoto
0 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-11 10:17 UTC (permalink / raw)
To: Chen Wang, Inochi Amaoto, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Richard Cochran, Longbin Li
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
On Wed, Jun 11, 2025 at 05:53:54PM +0800, Chen Wang wrote:
> "sophgo,sg2044-pwm" should have not been in 6.16, submit this after that?
>
It is merged for 6.17. So I think it is OK to go.
Regard,
Inochi
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices
2025-06-08 23:28 [PATCH 00/11] riscv: sophgo: sg2044: add DTS support for all available devices Inochi Amaoto
` (10 preceding siblings ...)
2025-06-08 23:28 ` [PATCH 11/11] riscv: dts: sophgo: add pwm controller for SG2044 Inochi Amaoto
@ 2025-06-17 5:07 ` Inochi Amaoto
11 siblings, 0 replies; 15+ messages in thread
From: Inochi Amaoto @ 2025-06-17 5:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Richard Cochran, Longbin Li, Inochi Amaoto
Cc: Han Gao, devicetree, linux-riscv, sophgo, linux-kernel, netdev,
Yixun Lan
On Mon, 09 Jun 2025 07:28:24 +0800, Inochi Amaoto wrote:
> As the clock driver for SG2044 got merged, it is possible to add
> dts node for all support devices of SG2044.
>
> Inochi Amaoto (9):
> riscv: dts: sophgo: sg2044: Add system controller device
> riscv: dts: sophgo: sg2044: Add clock controller device
> riscv: dts: sophgo: sg2044: Add GPIO device
> riscv: dts: sophgo: sg2044: Add I2C device
> riscv: dts: sophgo: sg2044: add DMA controller device
> riscv: dts: sophgo: sg2044: Add MMC controller device
> riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device
> riscv: dts: sophgo: sg2044: Add ethernet control device
> riscv: dts: sophgo: sg2044: Add pinctrl device
>
> [...]
Applied to for-next, thanks!
[01/11] riscv: dts: sophgo: sg2044: Add system controller device
https://github.com/sophgo/linux/commit/50fa2633c143d857a68128da387e0bb09c6cd362
[02/11] riscv: dts: sophgo: sg2044: Add clock controller device
https://github.com/sophgo/linux/commit/acd836a65b8cdebb007df0c3e08ac5710f0994e7
[03/11] riscv: dts: sophgo: sg2044: Add GPIO device
https://github.com/sophgo/linux/commit/8fc13510b3540481d291e28172b41b571ea078c2
[04/11] riscv: dts: sophgo: sg2044: Add I2C device
https://github.com/sophgo/linux/commit/b0d0b60bc906160aa3a1654de82c24bd55a801b3
[05/11] riscv: dts: sophgo: sg2044: add DMA controller device
https://github.com/sophgo/linux/commit/e40105024f078269a9729f7488945c11f4f3422e
[06/11] riscv: dts: sophgo: sg2044: Add MMC controller device
https://github.com/sophgo/linux/commit/4a678cc75d580a6478bcfae60907fa732d485368
[07/11] riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device
https://github.com/sophgo/linux/commit/62d6db9792ff7ddec27a61df8223395b22860c0d
[08/11] riscv: dts: sophgo: sg2044: Add ethernet control device
https://github.com/sophgo/linux/commit/67970c99f040c3e26677178f323993ddf11cab1c
[09/11] riscv: dts: sophgo: sg2044: Add pinctrl device
https://github.com/sophgo/linux/commit/d32d3c657f4f8b45ace6dbdb48ad602fc9a44be8
[10/11] riscv: dts: sophgo: add SG2044 SPI NOR controller driver
https://github.com/sophgo/linux/commit/502ade8b6fd981ba3694000e684686954d73c3bb
[11/11] riscv: dts: sophgo: add pwm controller for SG2044
https://github.com/sophgo/linux/commit/ea389214c01b2767ed2bbd4e9a03573394b33fd3
Thanks,
Inochi
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