From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Kees Cook <kees@kernel.org>,
"Gustavo A . R . Silva" <gustavoars@kernel.org>,
Richard Cochran <richardcochran@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-hardening@vger.kernel.org, netdev@vger.kernel.org,
Sia Jee Heng <jeeheng.sia@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v2 11/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator
Date: Thu, 7 May 2026 22:36:21 -0700 [thread overview]
Message-ID: <20260508053632.818548-12-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260508053632.818548-1-changhuang.liang@starfivetech.com>
Add bindings for the Peripheral-0 clock and reset generator (PER0CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clock/starfive,jhb100-per0crg.yaml | 70 +++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 281 ++++++++++++++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 77 +++++
3 files changed, 428 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml
new file mode 100644
index 000000000000..d3d426a741cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-per0crg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-0 Clock and Reset Generator
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jhb100-per0crg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (25 MHz)
+ - description: PLL6
+ - description: Configure 400MHz
+ - description: Configure 800MHZ
+ - description: Non Coherent NOC Initiator
+ - description: Non Coherent NOC Target
+
+ clock-names:
+ items:
+ - const: osc
+ - const: pll6
+ - const: cfg_400
+ - const: cfg_800
+ - const: ncnoc_init
+ - const: ncnoc_targ
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@11a08000 {
+ compatible = "starfive,jhb100-per0crg";
+ reg = <0x11a08000 0x1000>;
+ clocks = <&osc>, <&pll6>, <&sys0crg 71>,
+ <&sys0crg 72>, <&sys0crg 70>,
+ <&sys2crg 23>;
+ clock-names = "osc", "pll6", "cfg_400",
+ "cfg_800", "ncnoc_init",
+ "ncnoc_targ";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index d19618e2a846..add2cd093dbd 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -106,4 +106,285 @@
#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0 32
#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 33
+/* PER0CRG clocks */
+#define JHB100_PER0CLK_CDR_I3C0 0
+#define JHB100_PER0CLK_CDR_I3C1 1
+#define JHB100_PER0CLK_CDR_I3C2 2
+#define JHB100_PER0CLK_CDR_I3C3 3
+#define JHB100_PER0CLK_CDR_I3C4 4
+#define JHB100_PER0CLK_CDR_I3C5 5
+#define JHB100_PER0CLK_CDR_I3C6 6
+#define JHB100_PER0CLK_CDR_I3C7 7
+#define JHB100_PER0CLK_CDR_I3C8 8
+#define JHB100_PER0CLK_CDR_I3C9 9
+#define JHB100_PER0CLK_CDR_I3C10 10
+#define JHB100_PER0CLK_CDR_I3C11 11
+#define JHB100_PER0CLK_CDR_I3C12 12
+#define JHB100_PER0CLK_CDR_I3C13 13
+#define JHB100_PER0CLK_CDR_I3C14 14
+#define JHB100_PER0CLK_CDR_I3C15 15
+#define JHB100_PER0CLK_200 16
+#define JHB100_PER0CLK_600_DIV6 17
+#define JHB100_PER0CLK_600_DIV6_DIV5 18
+#define JHB100_PER0CLK_TIMER0_DUALTIMER0 19
+#define JHB100_PER0CLK_TIMER1_DUALTIMER0 20
+#define JHB100_PER0CLK_TIMER0_DUALTIMER1 21
+#define JHB100_PER0CLK_TIMER1_DUALTIMER1 22
+#define JHB100_PER0CLK_TIMER0_DUALTIMER2 23
+#define JHB100_PER0CLK_TIMER1_DUALTIMER2 24
+#define JHB100_PER0CLK_1200_PH0_LVDS0 25
+#define JHB100_PER0CLK_1200_PH0_LVDS1 26
+#define JHB100_PER0CLK_1200_CORE0 27
+#define JHB100_PER0CLK_1200_CORE1 28
+#define JHB100_PER0CLK_1200_SHIFT90_LVDS0 29
+#define JHB100_PER0CLK_1200_SHIFT90_LVDS1 30
+#define JHB100_PER0CLK_1200_DIV5_CORE0 31
+#define JHB100_PER0CLK_1200_DIV5_CORE1 32
+#define JHB100_PER0CLK_PH0_LTPI0 33
+
+#define JHB100_PER0CLK_PH0_LTPI1 35
+
+#define JHB100_PER0CLK_PH90_LTPI0 37
+
+#define JHB100_PER0CLK_PH90_LTPI1 39
+
+#define JHB100_PER0CLK_240_CORE_LTPI0 41
+
+#define JHB100_PER0CLK_240_CORE_LTPI1 43
+
+#define JHB100_PER0CLK_AXI_DMA_I2C_INIT 45
+#define JHB100_PER0CLK_AXI_DMA_I3C_INIT 46
+#define JHB100_PER0CLK_AXI_DMA_UART_INIT 47
+#define JHB100_PER0CLK_CORE_DMAC0 48
+#define JHB100_PER0CLK_CORE_DMAC1 49
+#define JHB100_PER0CLK_CORE_DMAC2 50
+
+#define JHB100_PER0CLK_HDR_TX_I3C0 78
+#define JHB100_PER0CLK_HDR_TX_I3C1 79
+#define JHB100_PER0CLK_HDR_TX_I3C2 80
+#define JHB100_PER0CLK_HDR_TX_I3C3 81
+#define JHB100_PER0CLK_HDR_TX_I3C4 82
+#define JHB100_PER0CLK_HDR_TX_I3C5 83
+#define JHB100_PER0CLK_HDR_TX_I3C6 84
+#define JHB100_PER0CLK_HDR_TX_I3C7 85
+#define JHB100_PER0CLK_HDR_TX_I3C8 86
+#define JHB100_PER0CLK_HDR_TX_I3C9 87
+#define JHB100_PER0CLK_HDR_TX_I3C10 88
+#define JHB100_PER0CLK_HDR_TX_I3C11 89
+#define JHB100_PER0CLK_HDR_TX_I3C12 90
+#define JHB100_PER0CLK_HDR_TX_I3C13 91
+#define JHB100_PER0CLK_HDR_TX_I3C14 92
+#define JHB100_PER0CLK_HDR_TX_I3C15 93
+#define JHB100_PER0CLK_CORE_I2C0 94
+#define JHB100_PER0CLK_CORE_I2C1 95
+#define JHB100_PER0CLK_CORE_I2C2 96
+#define JHB100_PER0CLK_CORE_I2C3 97
+#define JHB100_PER0CLK_CORE_I2C4 98
+#define JHB100_PER0CLK_CORE_I2C5 99
+#define JHB100_PER0CLK_CORE_I2C6 100
+#define JHB100_PER0CLK_CORE_I2C7 101
+#define JHB100_PER0CLK_CORE_I2C8 102
+#define JHB100_PER0CLK_CORE_I2C9 103
+#define JHB100_PER0CLK_CORE_I2C10 104
+#define JHB100_PER0CLK_CORE_I2C11 105
+#define JHB100_PER0CLK_CORE_I2C12 106
+#define JHB100_PER0CLK_CORE_I2C13 107
+#define JHB100_PER0CLK_CORE_I2C14 108
+#define JHB100_PER0CLK_CORE_I2C15 109
+
+#define JHB100_PER0CLK_WDOGCLK_WDT0 126
+#define JHB100_PER0CLK_WDOGCLK_WDT1 127
+#define JHB100_PER0CLK_WDOGCLK_WDT2 128
+#define JHB100_PER0CLK_WDOGCLK_WDT3 129
+#define JHB100_PER0CLK_WDOGCLK_WDT_EXTERNAL 130
+#define JHB100_PER0CLK_SCLK_UART4 131
+#define JHB100_PER0CLK_SCLK_UART5 132
+#define JHB100_PER0CLK_SCLK_UART6 133
+#define JHB100_PER0CLK_SCLK_UART7 134
+#define JHB100_PER0CLK_SCLK_UART8 135
+#define JHB100_PER0CLK_SCLK_UART9 136
+#define JHB100_PER0CLK_SCLK_UART10 137
+#define JHB100_PER0CLK_SCLK_UART11 138
+#define JHB100_PER0CLK_SCLK_UART12 139
+#define JHB100_PER0CLK_SCLK_UART13 140
+#define JHB100_PER0CLK_SCLK_UART14 141
+
+#define JHB100_PER0CLK_PCLK_DMA_UART_CFG 148
+#define JHB100_PER0CLK_PCLK_DMA_I2C_CFG 149
+#define JHB100_PER0CLK_PCLK_DMA_I3C_CFG 150
+#define JHB100_PER0CLK_PCLK_DUALTIMER0 151
+#define JHB100_PER0CLK_PCLK_DUALTIMER1 152
+#define JHB100_PER0CLK_PCLK_DUALTIMER2 153
+
+#define JHB100_PER0CLK_HCLK_TRNG 156
+#define JHB100_PER0CLK_APB_I2C0 157
+#define JHB100_PER0CLK_APB_I2C1 158
+#define JHB100_PER0CLK_APB_I2C2 159
+#define JHB100_PER0CLK_APB_I2C3 160
+#define JHB100_PER0CLK_APB_I2C4 161
+#define JHB100_PER0CLK_APB_I2C5 162
+#define JHB100_PER0CLK_APB_I2C6 163
+#define JHB100_PER0CLK_APB_I2C7 164
+#define JHB100_PER0CLK_APB_I2C8 165
+#define JHB100_PER0CLK_APB_I2C9 166
+#define JHB100_PER0CLK_APB_I2C10 167
+#define JHB100_PER0CLK_APB_I2C11 168
+#define JHB100_PER0CLK_APB_I2C12 169
+#define JHB100_PER0CLK_APB_I2C13 170
+#define JHB100_PER0CLK_APB_I2C14 171
+#define JHB100_PER0CLK_APB_I2C15 172
+#define JHB100_PER0CLK_APB_I2CF0 173
+#define JHB100_PER0CLK_APB_I2CF1 174
+#define JHB100_PER0CLK_APB_I2CF2 175
+#define JHB100_PER0CLK_APB_I2CF3 176
+#define JHB100_PER0CLK_APB_I2CF4 177
+#define JHB100_PER0CLK_APB_I2CF5 178
+#define JHB100_PER0CLK_APB_I2CF6 179
+#define JHB100_PER0CLK_APB_I2CF7 180
+#define JHB100_PER0CLK_APB_I2CF8 181
+#define JHB100_PER0CLK_APB_I2CF9 182
+#define JHB100_PER0CLK_APB_I2CF10 183
+#define JHB100_PER0CLK_APB_I2CF11 184
+#define JHB100_PER0CLK_APB_I2CF12 185
+#define JHB100_PER0CLK_APB_I2CF13 186
+#define JHB100_PER0CLK_APB_I2CF14 187
+#define JHB100_PER0CLK_APB_I2CF15 188
+#define JHB100_PER0CLK_APB_I3C0 189
+#define JHB100_PER0CLK_APB_I3C1 190
+#define JHB100_PER0CLK_APB_I3C2 191
+#define JHB100_PER0CLK_APB_I3C3 192
+#define JHB100_PER0CLK_APB_I3C4 193
+#define JHB100_PER0CLK_APB_I3C5 194
+#define JHB100_PER0CLK_APB_I3C6 195
+#define JHB100_PER0CLK_APB_I3C7 196
+#define JHB100_PER0CLK_APB_I3C8 197
+#define JHB100_PER0CLK_APB_I3C9 198
+#define JHB100_PER0CLK_APB_I3C10 199
+#define JHB100_PER0CLK_APB_I3C11 200
+#define JHB100_PER0CLK_APB_I3C12 201
+#define JHB100_PER0CLK_APB_I3C13 202
+#define JHB100_PER0CLK_APB_I3C14 203
+#define JHB100_PER0CLK_APB_I3C15 204
+#define JHB100_PER0CLK_APB_UART0 205
+#define JHB100_PER0CLK_APB_UART1 206
+#define JHB100_PER0CLK_APB_UART2 207
+#define JHB100_PER0CLK_APB_UART3 208
+#define JHB100_PER0CLK_APB_UART4 209
+#define JHB100_PER0CLK_APB_UART5 210
+#define JHB100_PER0CLK_APB_UART6 211
+#define JHB100_PER0CLK_APB_UART7 212
+#define JHB100_PER0CLK_APB_UART8 213
+#define JHB100_PER0CLK_APB_UART9 214
+#define JHB100_PER0CLK_APB_UART10 215
+#define JHB100_PER0CLK_APB_UART11 216
+#define JHB100_PER0CLK_APB_UART12 217
+#define JHB100_PER0CLK_APB_UART13 218
+#define JHB100_PER0CLK_APB_UART14 219
+#define JHB100_PER0CLK_DMA_I3C0 220
+#define JHB100_PER0CLK_DMA_I3C1 221
+#define JHB100_PER0CLK_DMA_I3C2 222
+#define JHB100_PER0CLK_DMA_I3C3 223
+#define JHB100_PER0CLK_DMA_I3C4 224
+#define JHB100_PER0CLK_DMA_I3C5 225
+#define JHB100_PER0CLK_DMA_I3C6 226
+#define JHB100_PER0CLK_DMA_I3C7 227
+#define JHB100_PER0CLK_DMA_I3C8 228
+#define JHB100_PER0CLK_DMA_I3C9 229
+#define JHB100_PER0CLK_DMA_I3C10 230
+#define JHB100_PER0CLK_DMA_I3C11 231
+#define JHB100_PER0CLK_DMA_I3C12 232
+#define JHB100_PER0CLK_DMA_I3C13 233
+#define JHB100_PER0CLK_DMA_I3C14 234
+#define JHB100_PER0CLK_DMA_I3C15 235
+#define JHB100_PER0CLK_CORE_I3C0 236
+#define JHB100_PER0CLK_CORE_I3C1 237
+#define JHB100_PER0CLK_CORE_I3C2 238
+#define JHB100_PER0CLK_CORE_I3C3 239
+#define JHB100_PER0CLK_CORE_I3C4 240
+#define JHB100_PER0CLK_CORE_I3C5 241
+#define JHB100_PER0CLK_CORE_I3C6 242
+#define JHB100_PER0CLK_CORE_I3C7 243
+#define JHB100_PER0CLK_CORE_I3C8 244
+#define JHB100_PER0CLK_CORE_I3C9 245
+#define JHB100_PER0CLK_CORE_I3C10 246
+#define JHB100_PER0CLK_CORE_I3C11 247
+#define JHB100_PER0CLK_CORE_I3C12 248
+#define JHB100_PER0CLK_CORE_I3C13 249
+#define JHB100_PER0CLK_CORE_I3C14 250
+#define JHB100_PER0CLK_CORE_I3C15 251
+#define JHB100_PER0CLK_DMAC_AXI_PERIPH0_HS_CLK_I2C 252
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C0 253
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C1 254
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C2 255
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C3 256
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C4 257
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C5 258
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C6 259
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C7 260
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C8 261
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C9 262
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C10 263
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C11 264
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C12 265
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C13 266
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C14 267
+#define JHB100_PER0CLK_MAIN_ICG_EN_I3C15 268
+#define JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER0 269
+#define JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER1 270
+#define JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER2 271
+#define JHB100_PER0CLK_MAIN_ICG_EN_LTPI0 272
+#define JHB100_PER0CLK_MAIN_ICG_EN_LTPI1 273
+#define JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I2C 274
+#define JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I3C 275
+#define JHB100_PER0CLK_MAIN_ICG_EN_DMAC_UART 276
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL4 277
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL5 278
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL6 279
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL7 280
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL8 281
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL9 282
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL10 283
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL11 284
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL12 285
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL13 286
+#define JHB100_PER0CLK_MAIN_ICG_EN_SOL14 287
+
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C0 304
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C1 305
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C2 306
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C3 307
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C4 308
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C5 309
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C6 310
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C7 311
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C8 312
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C9 313
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C10 314
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C11 315
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C12 316
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C13 317
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C14 318
+#define JHB100_PER0CLK_MAIN_ICG_EN_I2C15 319
+#define JHB100_PER0CLK_MAIN_ICG_EN_WDT0 320
+#define JHB100_PER0CLK_MAIN_ICG_EN_WDT1 321
+#define JHB100_PER0CLK_MAIN_ICG_EN_WDT2 322
+#define JHB100_PER0CLK_MAIN_ICG_EN_WDT3 323
+#define JHB100_PER0CLK_MAIN_ICG_EN_WDT_EXTERNAL 324
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART4 325
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART5 326
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART6 327
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART7 328
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART8 329
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART9 330
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART10 331
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART11 332
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART12 333
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART13 334
+#define JHB100_PER0CLK_MAIN_ICG_EN_UART14 335
+#define JHB100_PER0CLK_MAIN_ICG_EN_LDO0 336
+#define JHB100_PER0CLK_MAIN_ICG_EN_LDO1 337
+#define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_PERIPH0 338
+#define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_DMAC 339
+#define JHB100_PER0CLK_MAIN_ICG_EN_TRNG 340
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index fbc55f95e76c..ccfb7616e1a7 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -61,4 +61,81 @@
#define JHB100_SYS2RST_GPU1_RSTN_BUS 21
#define JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N 22
+/* PER0CRG resets */
+#define JHB100_PER0RST_MAIN_RSTN_UART4 0
+#define JHB100_PER0RST_MAIN_RSTN_UART5 1
+#define JHB100_PER0RST_MAIN_RSTN_UART6 2
+#define JHB100_PER0RST_MAIN_RSTN_UART7 3
+#define JHB100_PER0RST_MAIN_RSTN_UART8 4
+#define JHB100_PER0RST_MAIN_RSTN_UART9 5
+#define JHB100_PER0RST_MAIN_RSTN_UART10 6
+#define JHB100_PER0RST_MAIN_RSTN_UART11 7
+#define JHB100_PER0RST_MAIN_RSTN_UART12 8
+#define JHB100_PER0RST_MAIN_RSTN_UART13 9
+#define JHB100_PER0RST_MAIN_RSTN_UART14 10
+#define JHB100_PER0RST_MAIN_RSTN_I2C0 11
+#define JHB100_PER0RST_MAIN_RSTN_I2C1 12
+#define JHB100_PER0RST_MAIN_RSTN_I2C2 13
+#define JHB100_PER0RST_MAIN_RSTN_I2C3 14
+#define JHB100_PER0RST_MAIN_RSTN_I2C4 15
+#define JHB100_PER0RST_MAIN_RSTN_I2C5 16
+#define JHB100_PER0RST_MAIN_RSTN_I2C6 17
+#define JHB100_PER0RST_MAIN_RSTN_I2C7 18
+#define JHB100_PER0RST_MAIN_RSTN_I2C8 19
+#define JHB100_PER0RST_MAIN_RSTN_I2C9 20
+#define JHB100_PER0RST_MAIN_RSTN_I2C10 21
+#define JHB100_PER0RST_MAIN_RSTN_I2C11 22
+#define JHB100_PER0RST_MAIN_RSTN_I2C12 23
+#define JHB100_PER0RST_MAIN_RSTN_I2C13 24
+#define JHB100_PER0RST_MAIN_RSTN_I2C14 25
+#define JHB100_PER0RST_MAIN_RSTN_I2C15 26
+#define JHB100_PER0RST_MAIN_RSTN_I3C0 27
+#define JHB100_PER0RST_MAIN_RSTN_I3C1 28
+#define JHB100_PER0RST_MAIN_RSTN_I3C2 29
+#define JHB100_PER0RST_MAIN_RSTN_I3C3 30
+#define JHB100_PER0RST_MAIN_RSTN_I3C4 31
+#define JHB100_PER0RST_MAIN_RSTN_I3C5 32
+#define JHB100_PER0RST_MAIN_RSTN_I3C6 33
+#define JHB100_PER0RST_MAIN_RSTN_I3C7 34
+#define JHB100_PER0RST_MAIN_RSTN_I3C8 35
+#define JHB100_PER0RST_MAIN_RSTN_I3C9 36
+#define JHB100_PER0RST_MAIN_RSTN_I3C10 37
+#define JHB100_PER0RST_MAIN_RSTN_I3C11 38
+#define JHB100_PER0RST_MAIN_RSTN_I3C12 39
+#define JHB100_PER0RST_MAIN_RSTN_I3C13 40
+#define JHB100_PER0RST_MAIN_RSTN_I3C14 41
+#define JHB100_PER0RST_MAIN_RSTN_I3C15 42
+#define JHB100_PER0RST_MAIN_RSTN_WDT0 43
+#define JHB100_PER0RST_MAIN_RSTN_WDT1 44
+#define JHB100_PER0RST_MAIN_RSTN_WDT2 45
+#define JHB100_PER0RST_MAIN_RSTN_WDT3 46
+#define JHB100_PER0RST_MAIN_RSTN_WDT4 47
+#define JHB100_PER0RST_MAIN_RSTN_DUALTIMER0 48
+#define JHB100_PER0RST_MAIN_RSTN_DUALTIMER1 49
+#define JHB100_PER0RST_MAIN_RSTN_DUALTIMER2 50
+#define JHB100_PER0RST_MAIN_RSTN_TRNG 51
+#define JHB100_PER0RST_MAIN_RSTN_DMAC0 52
+#define JHB100_PER0RST_MAIN_RSTN_DMAC1 53
+#define JHB100_PER0RST_MAIN_RSTN_DMAC2 54
+#define JHB100_PER0RST_MAIN_RSTN_LTPI0 55
+#define JHB100_PER0RST_MAIN_RSTN_LTPI1 56
+#define JHB100_PER0RST_MAIN_RSTN_SOL4 57
+#define JHB100_PER0RST_MAIN_RSTN_SOL5 58
+#define JHB100_PER0RST_MAIN_RSTN_SOL6 59
+#define JHB100_PER0RST_MAIN_RSTN_SOL7 60
+#define JHB100_PER0RST_MAIN_RSTN_SOL8 61
+#define JHB100_PER0RST_MAIN_RSTN_SOL9 62
+#define JHB100_PER0RST_MAIN_RSTN_SOL10 63
+#define JHB100_PER0RST_MAIN_RSTN_SOL11 64
+#define JHB100_PER0RST_MAIN_RSTN_SOL12 65
+#define JHB100_PER0RST_MAIN_RSTN_SOL13 66
+#define JHB100_PER0RST_MAIN_RSTN_SOL14 67
+#define JHB100_PER0RST_MAIN_RSTN_LDO0 68
+#define JHB100_PER0RST_MAIN_RSTN_LDO1 69
+#define JHB100_PER0RST_MAIN_RSTN_PERIPH0_SENSORS 70
+#define JHB100_PER0RST_MAIN_RSTN_DMAC0_SENSORS 71
+#define JHB100_PER0RST_SYSCON_PRESETN 72
+#define JHB100_PER0RST_GPIO_IOMUX_PRESETN 73
+#define JHB100_PER0RST_UART_MUX_REG_WRAP 74
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2026-05-08 5:37 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 5:36 [PATCH v2 00/22] Add basic clocks and resets for JHB100 SoC Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 01/22] reset: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 02/22] reset: starfive: Convert the word "jh71x0" to "starfive" Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 03/22] clk: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 05/22] dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 06/22] clk: starfive: Add JHB100 System-0 clock generator driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 07/22] dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 08/22] clk: starfive: Add JHB100 System-1 clock generator driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 09/22] dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 10/22] clk: starfive: Add JHB100 System-2 clock generator driver Changhuang Liang
2026-05-08 5:36 ` Changhuang Liang [this message]
2026-05-08 5:36 ` [PATCH v2 12/22] clk: starfive: Introduce inverter and divider Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 13/22] clk: starfive: Expand the storage of clock parent index Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 14/22] clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 15/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 16/22] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 17/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator Changhuang Liang
2026-05-08 6:46 ` Rob Herring (Arm)
2026-05-08 5:36 ` [PATCH v2 18/22] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 19/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 20/22] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 21/22] reset: starfive: Add StarFive JHB100 reset driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes Changhuang Liang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260508053632.818548-12-changhuang.liang@starfivetech.com \
--to=changhuang.liang@starfivetech.com \
--cc=alex@ghiti.fr \
--cc=aou@eecs.berkeley.edu \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=gustavoars@kernel.org \
--cc=hal.feng@starfivetech.com \
--cc=jeeheng.sia@starfivetech.com \
--cc=kees@kernel.org \
--cc=kernel@esmil.dk \
--cc=krzk+dt@kernel.org \
--cc=leyfoon.tan@starfivetech.com \
--cc=linux-clk@vger.kernel.org \
--cc=linux-hardening@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mturquette@baylibre.com \
--cc=netdev@vger.kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=pjw@kernel.org \
--cc=richardcochran@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox