From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Kees Cook <kees@kernel.org>,
"Gustavo A . R . Silva" <gustavoars@kernel.org>,
Richard Cochran <richardcochran@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-hardening@vger.kernel.org, netdev@vger.kernel.org,
Sia Jee Heng <jeeheng.sia@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v2 20/22] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver
Date: Thu, 7 May 2026 22:36:30 -0700 [thread overview]
Message-ID: <20260508053632.818548-21-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260508053632.818548-1-changhuang.liang@starfivetech.com>
Add driver for the StarFive JHB100 Peripheral-3 clock controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 ++
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per3.c | 136 ++++++++++++++++++
3 files changed, 145 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per3.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 01d6d325dcd0..c612f1ede7d7 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -97,6 +97,14 @@ config CLK_STARFIVE_JHB100_PER2
Say yes here to support the peripheral-2 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PER3
+ bool "StarFive JHB100 peripheral-3 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS1
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-3 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 044e1942ccfa..f00690f0cdad 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) += clk-starfive-jhb100-per3.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per3.c b/drivers/clk/starfive/clk-starfive-jhb100-per3.c
new file mode 100644
index 000000000000..23f6a3db655c
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per3.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-3 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-common.h"
+
+#define JHB100_PER3CLK_NUM_CLKS (JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 + 1)
+
+/* external clocks */
+#define JHB100_PER3CLK_NCNOC_INIT (JHB100_PER3CLK_NUM_CLKS + 0)
+#define JHB100_PER3CLK_NCNOC_TARG (JHB100_PER3CLK_NUM_CLKS + 1)
+#define JHB100_PER3CLK_CFG_125 (JHB100_PER3CLK_NUM_CLKS + 2)
+#define JHB100_PER3CLK_GMAC0_RMII_RCLKI (JHB100_PER3CLK_NUM_CLKS + 3)
+#define JHB100_PER3CLK_GMAC1_SGMII_TX (JHB100_PER3CLK_NUM_CLKS + 4)
+#define JHB100_PER3CLK_GMAC1_SGMII_RX (JHB100_PER3CLK_NUM_CLKS + 5)
+#define JHB100_PER3CLK_OSC (JHB100_PER3CLK_NUM_CLKS + 6)
+
+char *jhb100_per3_ext_clk[] = {
+ "ncnoc_init",
+ "ncnoc_targ",
+ "cfg_125",
+ "gmac0_rmii_rclki",
+ "gmac1_sgmii_tx",
+ "gmac1_sgmii_rx",
+ "osc",
+};
+
+static const struct starfive_clk_data jhb100_per3crg_clk_data[] = {
+ STARFIVE__DIV(JHB100_PER3CLK_300, "per3_300", 256,
+ JHB100_PER3CLK_NCNOC_INIT),
+ STARFIVE__DIV(JHB100_PER3CLK_200, "per3_200", 256,
+ JHB100_PER3CLK_NCNOC_INIT),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC1_PTP_REF, "gmac1_ptp_ref", 2,
+ JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE__MUX(JHB100_PER3CLK_GMAC1_TX_125_MUX, "gmac1_tx_125_mux", 0, 2,
+ JHB100_PER3CLK_GMAC1_SGMII_TX,
+ JHB100_PER3CLK_CFG_125),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC1_TX, "gmac1_tx", 50,
+ JHB100_PER3CLK_GMAC1_TX_125_MUX),
+ STARFIVE__MUX(JHB100_PER3CLK_GMAC1_RX_125_MUX, "gmac1_rx_125_mux", 0, 2,
+ JHB100_PER3CLK_GMAC1_SGMII_RX,
+ JHB100_PER3CLK_CFG_125),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC1_RX, "gmac1_rx", 50,
+ JHB100_PER3CLK_GMAC1_RX_125_MUX),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC0_PTP_REF, "gmac0_ptp_ref", 2,
+ JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC0_RMII_PLL, "gmac0_rmii_pll", 2,
+ JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE__MUX(JHB100_PER3CLK_GMAC0_RMII_MUX, "gmac0_rmii_mux", 0, 2,
+ JHB100_PER3CLK_GMAC0_RMII_PLL,
+ JHB100_PER3CLK_GMAC0_RMII_RCLKI),
+ STARFIVE__DIV(JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2, "gmac0_rmii_mux_div2", 20,
+ JHB100_PER3CLK_GMAC0_RMII_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I, "ether0_rmii_clk_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I, "ether0_rmii_clk_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I, "ether0_rmii_clk_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_PTP_REF),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I, "ether0_rmii_clk_rmii_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I, "ether0_rmii_clk_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_RMII_ACLK_I, "ether0_rmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_300),
+ STARFIVE_GATE(JHB100_PER3CLK_GMAC0_RMII_RCLKO, "gmac0_rmii_rclko",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC0_RMII_PLL),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I, "ether0_sgmii_clk_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I, "ether0_sgmii_clk_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I, "ether0_sgmii_clk_tx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_TX_125_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I, "ether0_sgmii_clk_rx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_RX_125_MUX),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I, "ether0_sgmii_clk_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_GMAC1_PTP_REF),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I, "ether0_sgmii_clk_ref_25_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_OSC),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I, "ether0_sgmii_clk_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_ACLK_I, "ether0_sgmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_300),
+ STARFIVE_GATE(JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I, "ether0_sgmii_phy_pclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3, "main_icg_en_sensors_periph3", 0,
+ JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI0, "main_icg_en_peci0", 0,
+ JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_PECI1, "main_icg_en_peci1", 0,
+ JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC0, "main_icg_en_gmac0",
+ CLK_IS_CRITICAL, JHB100_PER3CLK_NCNOC_TARG),
+ STARFIVE_GATE(JHB100_PER3CLK_MAIN_ICG_EN_GMAC1, "main_icg_en_gmac1",
+ CLK_IS_CRITICAL, JHB100_PER3CLK_NCNOC_TARG),
+};
+
+const struct jhb100_crg_domain_info jhb100_per3crg_info = {
+ .clk_data = jhb100_per3crg_clk_data,
+ .num_clk = ARRAY_SIZE(jhb100_per3crg_clk_data),
+ .ext_clk = jhb100_per3_ext_clk,
+ .num_ext_clk = ARRAY_SIZE(jhb100_per3_ext_clk),
+ .rst_name = "jhb100-r-per3",
+ .power_domain = false,
+};
+
+static const struct of_device_id jhb100_per3crg_match[] = {
+ {
+ .compatible = "starfive,jhb100-per3crg",
+ .data = &jhb100_per3crg_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per3crg_match);
+
+static struct platform_driver jhb100_per3crg_driver = {
+ .probe = starfive_crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per3",
+ .of_match_table = jhb100_per3crg_match,
+ },
+};
+module_platform_driver(jhb100_per3crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-3 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
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next prev parent reply other threads:[~2026-05-08 5:37 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 5:36 [PATCH v2 00/22] Add basic clocks and resets for JHB100 SoC Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 01/22] reset: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 02/22] reset: starfive: Convert the word "jh71x0" to "starfive" Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 03/22] clk: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 05/22] dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 06/22] clk: starfive: Add JHB100 System-0 clock generator driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 07/22] dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 08/22] clk: starfive: Add JHB100 System-1 clock generator driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 09/22] dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 10/22] clk: starfive: Add JHB100 System-2 clock generator driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 11/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 12/22] clk: starfive: Introduce inverter and divider Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 13/22] clk: starfive: Expand the storage of clock parent index Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 14/22] clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 15/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 16/22] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 17/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator Changhuang Liang
2026-05-08 6:46 ` Rob Herring (Arm)
2026-05-08 5:36 ` [PATCH v2 18/22] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 19/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` Changhuang Liang [this message]
2026-05-08 5:36 ` [PATCH v2 21/22] reset: starfive: Add StarFive JHB100 reset driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes Changhuang Liang
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