From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Kees Cook <kees@kernel.org>,
"Gustavo A . R . Silva" <gustavoars@kernel.org>,
Richard Cochran <richardcochran@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-hardening@vger.kernel.org, netdev@vger.kernel.org,
Sia Jee Heng <jeeheng.sia@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v2 07/22] dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator
Date: Thu, 7 May 2026 22:36:17 -0700 [thread overview]
Message-ID: <20260508053632.818548-8-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260508053632.818548-1-changhuang.liang@starfivetech.com>
Add bindings for the System-1 clocks and reset generator (SYS1CRG) on
JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clock/starfive,jhb100-sys1crg.yaml | 71 +++++++++++++++++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 20 ++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 11 +++
3 files changed, 102 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml
new file mode 100644
index 000000000000..627dfb8593a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys1crg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-1 Clock and Reset Generator
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jhb100-sys1crg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (25 MHz)
+ - description: PLL0
+ - description: PLL1
+ - description: PLL2
+ - description: PLL4
+ - description: PLL5
+ - description: NPU Non Coherent NOC Initiator
+
+ clock-names:
+ items:
+ - const: osc
+ - const: pll0
+ - const: pll1
+ - const: pll2
+ - const: pll4
+ - const: pll5
+ - const: npu_ncnoc_init
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@13004000 {
+ compatible = "starfive,jhb100-sys1crg";
+ reg = <0x13004000 0x4000>;
+ clocks = <&osc>, <&pll0>, <&pll1>,
+ <&syspll 0>, <&syspll 2>,
+ <&syspll 3>, <&sys0crg 61>;
+ clock-names = "osc", "pll0", "pll1", "pll2",
+ "pll4", "pll5", "npu_ncnoc_init";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 24ef2663f05a..d7904b32bd51 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -53,4 +53,24 @@
#define JHB100_SYS0CLK_GPU0_NCNOC_INIT 73
#define JHB100_SYS0CLK_GPU1_NCNOC_INIT 74
+/* SYS1CRG clocks */
+#define JHB100_SYS1CLK_APB_MAIN_SYS1 0
+#define JHB100_SYS1CLK_APB_SENSOR_ICG_BUF 1
+
+#define JHB100_SYS1CLK_GPIO_ESPI1_EXT 5
+
+#define JHB100_SYS1CLK_HOSTSS1_NCNOC_CFG 7
+#define JHB100_SYS1CLK_HOSTSS1_PHY_SCAN_1000_ICG_BUF 8
+#define JHB100_SYS1CLK_NPU_NCNOC_CFG 9
+#define JHB100_SYS1CLK_NPU_CORE_DIV 10
+#define JHB100_SYS1CLK_DOM_NPU_CORE_CLK 11
+#define JHB100_SYS1CLK_DOM_NPU_BUS_CLK 12
+#define JHB100_SYS1CLK_DOM_NPU_INIT_CLK 13
+#define JHB100_SYS1CLK_DOM_NPU_OSC_CLK 14
+#define JHB100_SYS1CLK_VOUT_NCNOC_TARG 15
+#define JHB100_SYS1CLK_VOUT_PIX0 16
+#define JHB100_SYS1CLK_VOUT_PIX1 17
+#define JHB100_SYS1CLK_BMCPER3_NCNOC_TARG 18
+#define JHB100_SYS1CLK_BMCPER3_CFG_125 19
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index 5c7b00afda73..da1b51621172 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -25,4 +25,15 @@
#define JHB100_SYS0RST_BMCUSB_RSTN_BUS 13
#define JHB100_SYS0RST_BMCUSB_RSTN_CRG 14
+/* SYS1CRG resets */
+#define JHB100_SYS1RST_SYS1_IOMUX_PRESETN 0
+#define JHB100_SYS1RST_MAIN_RSTN_CHIPTOP_SENSOR 1
+#define JHB100_SYS1RST_VOUT_RSTN_HOST0 2
+#define JHB100_SYS1RST_VOUT_RSTN_HOST1 3
+#define JHB100_SYS1RST_HOSTSS1_RSTN_BUS_ESPI 4
+#define JHB100_SYS1RST_HOSTSS1_RSTN_BUS_PCIE 5
+#define JHB100_SYS1RST_HOSTSS1_RSTN_CRG 6
+#define JHB100_SYS1RST_BMCPERIPH3_RSTN_CRG 7
+#define JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS 8
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1
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next prev parent reply other threads:[~2026-05-08 5:37 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 5:36 [PATCH v2 00/22] Add basic clocks and resets for JHB100 SoC Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 01/22] reset: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 02/22] reset: starfive: Convert the word "jh71x0" to "starfive" Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 03/22] clk: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 05/22] dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 06/22] clk: starfive: Add JHB100 System-0 clock generator driver Changhuang Liang
2026-05-08 5:36 ` Changhuang Liang [this message]
2026-05-08 5:36 ` [PATCH v2 08/22] clk: starfive: Add JHB100 System-1 " Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 09/22] dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 10/22] clk: starfive: Add JHB100 System-2 clock generator driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 11/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 12/22] clk: starfive: Introduce inverter and divider Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 13/22] clk: starfive: Expand the storage of clock parent index Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 14/22] clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 15/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 16/22] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 17/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator Changhuang Liang
2026-05-08 6:46 ` Rob Herring (Arm)
2026-05-08 5:36 ` [PATCH v2 18/22] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 19/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 20/22] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 21/22] reset: starfive: Add StarFive JHB100 reset driver Changhuang Liang
2026-05-08 5:36 ` [PATCH v2 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes Changhuang Liang
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