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* [PATCH v2 0/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x
@ 2025-02-05 20:40 Palmer Dabbelt
  2025-02-05 20:40 ` [PATCH v2 1/2] RISC-V: hwprobe: Use BIT macro to avoid warnings Palmer Dabbelt
  2025-02-05 20:40 ` [PATCH v2 2/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
  0 siblings, 2 replies; 5+ messages in thread
From: Palmer Dabbelt @ 2025-02-05 20:40 UTC (permalink / raw)
  To: linux-riscv; +Cc: alex, Charlie Jenkins, Mr.Bossman075

This was way back in the patch queue and had some feedback.  I needed to
re-spin it to pick up the first patch anyway, so I figured I'd just do
the rest too.


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^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH v2 1/2] RISC-V: hwprobe: Use BIT macro to avoid warnings
  2025-02-05 20:40 [PATCH v2 0/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
@ 2025-02-05 20:40 ` Palmer Dabbelt
  2025-02-06  8:58   ` Andreas Schwab
  2025-02-05 20:40 ` [PATCH v2 2/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
  1 sibling, 1 reply; 5+ messages in thread
From: Palmer Dabbelt @ 2025-02-05 20:40 UTC (permalink / raw)
  To: linux-riscv
  Cc: alex, Charlie Jenkins, Mr.Bossman075, Jesse Taube, Palmer Dabbelt

From: Jesse Taube <jesse@rivosinc.com>

In uapi/asm/hwprobe.h file, (1 << N) is used to define the bit field
which causes checkpatch to warn. Use BIT(N) and BIT_ULL(N) to avoid
these warnings.

Signed-off-by: Jesse Taube <jesse@rivosinc.com>
[Palmer: rebase and clean up a bit]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/include/uapi/asm/hwprobe.h | 117 +++++++++++++-------------
 1 file changed, 59 insertions(+), 58 deletions(-)

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index c3c1cc951cb9..600ca96ae55e 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -7,6 +7,7 @@
 #define _UAPI_ASM_HWPROBE_H
 
 #include <linux/types.h>
+#include <linux/const.h>
 
 /*
  * Interface for probing hardware capabilities from userspace, see
@@ -21,65 +22,65 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_MARCHID	1
 #define RISCV_HWPROBE_KEY_MIMPID	2
 #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR	3
-#define		RISCV_HWPROBE_BASE_BEHAVIOR_IMA	(1 << 0)
+#define		RISCV_HWPROBE_BASE_BEHAVIOR_IMA	_BITULL(0)
 #define RISCV_HWPROBE_KEY_IMA_EXT_0	4
-#define		RISCV_HWPROBE_IMA_FD		(1 << 0)
-#define		RISCV_HWPROBE_IMA_C		(1 << 1)
-#define		RISCV_HWPROBE_IMA_V		(1 << 2)
-#define		RISCV_HWPROBE_EXT_ZBA		(1 << 3)
-#define		RISCV_HWPROBE_EXT_ZBB		(1 << 4)
-#define		RISCV_HWPROBE_EXT_ZBS		(1 << 5)
-#define		RISCV_HWPROBE_EXT_ZICBOZ	(1 << 6)
-#define		RISCV_HWPROBE_EXT_ZBC		(1 << 7)
-#define		RISCV_HWPROBE_EXT_ZBKB		(1 << 8)
-#define		RISCV_HWPROBE_EXT_ZBKC		(1 << 9)
-#define		RISCV_HWPROBE_EXT_ZBKX		(1 << 10)
-#define		RISCV_HWPROBE_EXT_ZKND		(1 << 11)
-#define		RISCV_HWPROBE_EXT_ZKNE		(1 << 12)
-#define		RISCV_HWPROBE_EXT_ZKNH		(1 << 13)
-#define		RISCV_HWPROBE_EXT_ZKSED		(1 << 14)
-#define		RISCV_HWPROBE_EXT_ZKSH		(1 << 15)
-#define		RISCV_HWPROBE_EXT_ZKT		(1 << 16)
-#define		RISCV_HWPROBE_EXT_ZVBB		(1 << 17)
-#define		RISCV_HWPROBE_EXT_ZVBC		(1 << 18)
-#define		RISCV_HWPROBE_EXT_ZVKB		(1 << 19)
-#define		RISCV_HWPROBE_EXT_ZVKG		(1 << 20)
-#define		RISCV_HWPROBE_EXT_ZVKNED	(1 << 21)
-#define		RISCV_HWPROBE_EXT_ZVKNHA	(1 << 22)
-#define		RISCV_HWPROBE_EXT_ZVKNHB	(1 << 23)
-#define		RISCV_HWPROBE_EXT_ZVKSED	(1 << 24)
-#define		RISCV_HWPROBE_EXT_ZVKSH		(1 << 25)
-#define		RISCV_HWPROBE_EXT_ZVKT		(1 << 26)
-#define		RISCV_HWPROBE_EXT_ZFH		(1 << 27)
-#define		RISCV_HWPROBE_EXT_ZFHMIN	(1 << 28)
-#define		RISCV_HWPROBE_EXT_ZIHINTNTL	(1 << 29)
-#define		RISCV_HWPROBE_EXT_ZVFH		(1 << 30)
-#define		RISCV_HWPROBE_EXT_ZVFHMIN	(1ULL << 31)
-#define		RISCV_HWPROBE_EXT_ZFA		(1ULL << 32)
-#define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)
-#define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)
-#define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)
-#define		RISCV_HWPROBE_EXT_ZIHINTPAUSE	(1ULL << 36)
-#define		RISCV_HWPROBE_EXT_ZVE32X	(1ULL << 37)
-#define		RISCV_HWPROBE_EXT_ZVE32F	(1ULL << 38)
-#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 39)
-#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 40)
-#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 41)
-#define		RISCV_HWPROBE_EXT_ZIMOP		(1ULL << 42)
-#define		RISCV_HWPROBE_EXT_ZCA		(1ULL << 43)
-#define		RISCV_HWPROBE_EXT_ZCB		(1ULL << 44)
-#define		RISCV_HWPROBE_EXT_ZCD		(1ULL << 45)
-#define		RISCV_HWPROBE_EXT_ZCF		(1ULL << 46)
-#define		RISCV_HWPROBE_EXT_ZCMOP		(1ULL << 47)
-#define		RISCV_HWPROBE_EXT_ZAWRS		(1ULL << 48)
-#define		RISCV_HWPROBE_EXT_SUPM		(1ULL << 49)
+#define		RISCV_HWPROBE_IMA_FD		_BITULL(0)
+#define		RISCV_HWPROBE_IMA_C		_BITULL(1)
+#define		RISCV_HWPROBE_IMA_V		_BITULL(2)
+#define		RISCV_HWPROBE_EXT_ZBA		_BITULL(3)
+#define		RISCV_HWPROBE_EXT_ZBB		_BITULL(4)
+#define		RISCV_HWPROBE_EXT_ZBS		_BITULL(5)
+#define		RISCV_HWPROBE_EXT_ZICBOZ	_BITULL(6)
+#define		RISCV_HWPROBE_EXT_ZBC		_BITULL(7)
+#define		RISCV_HWPROBE_EXT_ZBKB		_BITULL(8)
+#define		RISCV_HWPROBE_EXT_ZBKC		_BITULL(9)
+#define		RISCV_HWPROBE_EXT_ZBKX		_BITULL(10)
+#define		RISCV_HWPROBE_EXT_ZKND		_BITULL(11)
+#define		RISCV_HWPROBE_EXT_ZKNE		_BITULL(12)
+#define		RISCV_HWPROBE_EXT_ZKNH		_BITULL(13)
+#define		RISCV_HWPROBE_EXT_ZKSED		_BITULL(14)
+#define		RISCV_HWPROBE_EXT_ZKSH		_BITULL(15)
+#define		RISCV_HWPROBE_EXT_ZKT		_BITULL(16)
+#define		RISCV_HWPROBE_EXT_ZVBB		_BITULL(17)
+#define		RISCV_HWPROBE_EXT_ZVBC		_BITULL(18)
+#define		RISCV_HWPROBE_EXT_ZVKB		_BITULL(19)
+#define		RISCV_HWPROBE_EXT_ZVKG		_BITULL(20)
+#define		RISCV_HWPROBE_EXT_ZVKNED	_BITULL(21)
+#define		RISCV_HWPROBE_EXT_ZVKNHA	_BITULL(22)
+#define		RISCV_HWPROBE_EXT_ZVKNHB	_BITULL(23)
+#define		RISCV_HWPROBE_EXT_ZVKSED	_BITULL(24)
+#define		RISCV_HWPROBE_EXT_ZVKSH		_BITULL(25)
+#define		RISCV_HWPROBE_EXT_ZVKT		_BITULL(26)
+#define		RISCV_HWPROBE_EXT_ZFH		_BITULL(27)
+#define		RISCV_HWPROBE_EXT_ZFHMIN	_BITULL(28)
+#define		RISCV_HWPROBE_EXT_ZIHINTNTL	_BITULL(29)
+#define		RISCV_HWPROBE_EXT_ZVFH		_BITULL(30)
+#define		RISCV_HWPROBE_EXT_ZVFHMIN	_BITULL(31)
+#define		RISCV_HWPROBE_EXT_ZFA		_BITULL(32)
+#define		RISCV_HWPROBE_EXT_ZTSO		_BITULL(33)
+#define		RISCV_HWPROBE_EXT_ZACAS		_BITULL(34)
+#define		RISCV_HWPROBE_EXT_ZICOND	_BITULL(35)
+#define		RISCV_HWPROBE_EXT_ZIHINTPAUSE	_BITULL(36)
+#define		RISCV_HWPROBE_EXT_ZVE32X	_BITULL(37)
+#define		RISCV_HWPROBE_EXT_ZVE32F	_BITULL(38)
+#define		RISCV_HWPROBE_EXT_ZVE64X	_BITULL(39)
+#define		RISCV_HWPROBE_EXT_ZVE64F	_BITULL(40)
+#define		RISCV_HWPROBE_EXT_ZVE64D	_BITULL(41)
+#define		RISCV_HWPROBE_EXT_ZIMOP		_BITULL(42)
+#define		RISCV_HWPROBE_EXT_ZCA		_BITULL(43)
+#define		RISCV_HWPROBE_EXT_ZCB		_BITULL(44)
+#define		RISCV_HWPROBE_EXT_ZCD		_BITULL(45)
+#define		RISCV_HWPROBE_EXT_ZCF		_BITULL(46)
+#define		RISCV_HWPROBE_EXT_ZCMOP		_BITULL(47)
+#define		RISCV_HWPROBE_EXT_ZAWRS		_BITULL(48)
+#define		RISCV_HWPROBE_EXT_SUPM		_BITULL(49)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
-#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_SLOW		(2 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_FAST		(3 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_UNSUPPORTED	(4 << 0)
-#define		RISCV_HWPROBE_MISALIGNED_MASK		(7 << 0)
+#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	0
+#define		RISCV_HWPROBE_MISALIGNED_EMULATED	1
+#define		RISCV_HWPROBE_MISALIGNED_SLOW		2
+#define		RISCV_HWPROBE_MISALIGNED_FAST		3
+#define		RISCV_HWPROBE_MISALIGNED_UNSUPPORTED	4
+#define		RISCV_HWPROBE_MISALIGNED_MASK		7
 #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE	6
 #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS	7
 #define RISCV_HWPROBE_KEY_TIME_CSR_FREQ	8
@@ -98,6 +99,6 @@ struct riscv_hwprobe {
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */
-#define RISCV_HWPROBE_WHICH_CPUS	(1 << 0)
+#define RISCV_HWPROBE_WHICH_CPUS	BIT(0)
 
 #endif
-- 
2.45.2


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^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH v2 2/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x
  2025-02-05 20:40 [PATCH v2 0/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
  2025-02-05 20:40 ` [PATCH v2 1/2] RISC-V: hwprobe: Use BIT macro to avoid warnings Palmer Dabbelt
@ 2025-02-05 20:40 ` Palmer Dabbelt
  2025-02-06  6:15   ` Tomasz Jeznach
  1 sibling, 1 reply; 5+ messages in thread
From: Palmer Dabbelt @ 2025-02-05 20:40 UTC (permalink / raw)
  To: linux-riscv; +Cc: alex, Charlie Jenkins, Mr.Bossman075, Palmer Dabbelt

There were a few of these outside hwprobe, so I figured it was easier to
just clean them up too.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/include/asm/csr.h       | 10 +++++-----
 arch/riscv/include/asm/kasan.h     |  2 +-
 tools/arch/riscv/include/asm/csr.h | 20 ++++++++++----------
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 6fed42e37705..181867da7fe3 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -221,15 +221,15 @@
 
 /* Smstateen bits */
 #define SMSTATEEN0_AIA_IMSIC_SHIFT	58
-#define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
+#define SMSTATEEN0_AIA_IMSIC		BIT_ULL(SMSTATEEN0_AIA_IMSIC_SHIFT)
 #define SMSTATEEN0_AIA_SHIFT		59
-#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
+#define SMSTATEEN0_AIA			BIT_ULL(SMSTATEEN0_AIA_SHIFT)
 #define SMSTATEEN0_AIA_ISEL_SHIFT	60
-#define SMSTATEEN0_AIA_ISEL		(_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)
+#define SMSTATEEN0_AIA_ISEL		BIT_ULL(SMSTATEEN0_AIA_ISEL_SHIFT)
 #define SMSTATEEN0_HSENVCFG_SHIFT	62
-#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
+#define SMSTATEEN0_HSENVCFG		BIT_ULL(SMSTATEEN0_HSENVCFG_SHIFT)
 #define SMSTATEEN0_SSTATEEN0_SHIFT	63
-#define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
+#define SMSTATEEN0_SSTATEEN0		BIT_ULL(SMSTATEEN0_SSTATEEN0_SHIFT)
 
 /* mseccfg bits */
 #define MSECCFG_PMM			ENVCFG_PMM
diff --git a/arch/riscv/include/asm/kasan.h b/arch/riscv/include/asm/kasan.h
index e6a0071bdb56..70660f431f8f 100644
--- a/arch/riscv/include/asm/kasan.h
+++ b/arch/riscv/include/asm/kasan.h
@@ -25,7 +25,7 @@
  */
 #define KASAN_SHADOW_SCALE_SHIFT	3
 
-#define KASAN_SHADOW_SIZE	(UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT))
+#define KASAN_SHADOW_SIZE	BIT_ULL((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)
 /*
  * Depending on the size of the virtual address space, the region may not be
  * aligned on PGDIR_SIZE, so force its alignment to ease its population.
diff --git a/tools/arch/riscv/include/asm/csr.h b/tools/arch/riscv/include/asm/csr.h
index 0dfc09254f99..902d607c282e 100644
--- a/tools/arch/riscv/include/asm/csr.h
+++ b/tools/arch/riscv/include/asm/csr.h
@@ -203,16 +203,16 @@
 #define ENVCFG_FIOM			_AC(0x1, UL)
 
 /* Smstateen bits */
-#define SMSTATEEN0_AIA_IMSIC_SHIFT	58
-#define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
-#define SMSTATEEN0_AIA_SHIFT		59
-#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
-#define SMSTATEEN0_AIA_ISEL_SHIFT	60
-#define SMSTATEEN0_AIA_ISEL		(_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)
-#define SMSTATEEN0_HSENVCFG_SHIFT	62
-#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
-#define SMSTATEEN0_SSTATEEN0_SHIFT	63
-#define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
+#define SMSTATEEN0_AIA_IMSIC_SHIFT	BIT_ULL(58)
+#define SMSTATEEN0_AIA_IMSIC		BIT_ULL(SMSTATEEN0_AIA_IMSIC_SHIFT)
+#define SMSTATEEN0_AIA_SHIFT		BIT_ULL(59)
+#define SMSTATEEN0_AIA			BIT_ULL(SMSTATEEN0_AIA_SHIFT)
+#define SMSTATEEN0_AIA_ISEL_SHIFT	BIT_ULL(60)
+#define SMSTATEEN0_AIA_ISEL		BIT_ULL(SMSTATEEN0_AIA_ISEL_SHIFT)
+#define SMSTATEEN0_HSENVCFG_SHIFT	BIT_ULL(62)
+#define SMSTATEEN0_HSENVCFG		BIT_ULL(SMSTATEEN0_HSENVCFG_SHIFT)
+#define SMSTATEEN0_SSTATEEN0_SHIFT	BIT_ULL(63)
+#define SMSTATEEN0_SSTATEEN0		BIT_ULL(SMSTATEEN0_SSTATEEN0_SHIFT)
 
 /* symbolic CSR names: */
 #define CSR_CYCLE		0xc00
-- 
2.45.2


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^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x
  2025-02-05 20:40 ` [PATCH v2 2/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
@ 2025-02-06  6:15   ` Tomasz Jeznach
  0 siblings, 0 replies; 5+ messages in thread
From: Tomasz Jeznach @ 2025-02-06  6:15 UTC (permalink / raw)
  To: Palmer Dabbelt; +Cc: linux-riscv, alex, Charlie Jenkins, Mr.Bossman075

On Wed, Feb 05, 2025 at 12:40:27PM -0800, Palmer Dabbelt wrote:
> There were a few of these outside hwprobe, so I figured it was easier to
> just clean them up too.
> 
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
>  arch/riscv/include/asm/csr.h       | 10 +++++-----
>  arch/riscv/include/asm/kasan.h     |  2 +-
>  tools/arch/riscv/include/asm/csr.h | 20 ++++++++++----------
>  3 files changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 6fed42e37705..181867da7fe3 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -221,15 +221,15 @@
>  
>  /* Smstateen bits */
>  #define SMSTATEEN0_AIA_IMSIC_SHIFT	58
> -#define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
> +#define SMSTATEEN0_AIA_IMSIC		BIT_ULL(SMSTATEEN0_AIA_IMSIC_SHIFT)
>  #define SMSTATEEN0_AIA_SHIFT		59
> -#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
> +#define SMSTATEEN0_AIA			BIT_ULL(SMSTATEEN0_AIA_SHIFT)
>  #define SMSTATEEN0_AIA_ISEL_SHIFT	60
> -#define SMSTATEEN0_AIA_ISEL		(_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)
> +#define SMSTATEEN0_AIA_ISEL		BIT_ULL(SMSTATEEN0_AIA_ISEL_SHIFT)
>  #define SMSTATEEN0_HSENVCFG_SHIFT	62
> -#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
> +#define SMSTATEEN0_HSENVCFG		BIT_ULL(SMSTATEEN0_HSENVCFG_SHIFT)
>  #define SMSTATEEN0_SSTATEEN0_SHIFT	63
> -#define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
> +#define SMSTATEEN0_SSTATEEN0		BIT_ULL(SMSTATEEN0_SSTATEEN0_SHIFT)
>  
>  /* mseccfg bits */
>  #define MSECCFG_PMM			ENVCFG_PMM
> diff --git a/arch/riscv/include/asm/kasan.h b/arch/riscv/include/asm/kasan.h
> index e6a0071bdb56..70660f431f8f 100644
> --- a/arch/riscv/include/asm/kasan.h
> +++ b/arch/riscv/include/asm/kasan.h
> @@ -25,7 +25,7 @@
>   */
>  #define KASAN_SHADOW_SCALE_SHIFT	3
>  
> -#define KASAN_SHADOW_SIZE	(UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT))
> +#define KASAN_SHADOW_SIZE	BIT_ULL((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)
>  /*
>   * Depending on the size of the virtual address space, the region may not be
>   * aligned on PGDIR_SIZE, so force its alignment to ease its population.
> diff --git a/tools/arch/riscv/include/asm/csr.h b/tools/arch/riscv/include/asm/csr.h
> index 0dfc09254f99..902d607c282e 100644
> --- a/tools/arch/riscv/include/asm/csr.h
> +++ b/tools/arch/riscv/include/asm/csr.h
> @@ -203,16 +203,16 @@
>  #define ENVCFG_FIOM			_AC(0x1, UL)
>  
>  /* Smstateen bits */
> -#define SMSTATEEN0_AIA_IMSIC_SHIFT	58
> -#define SMSTATEEN0_AIA_IMSIC		(_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
> -#define SMSTATEEN0_AIA_SHIFT		59
> -#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
> -#define SMSTATEEN0_AIA_ISEL_SHIFT	60
> -#define SMSTATEEN0_AIA_ISEL		(_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)
> -#define SMSTATEEN0_HSENVCFG_SHIFT	62
> -#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
> -#define SMSTATEEN0_SSTATEEN0_SHIFT	63
> -#define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
> +#define SMSTATEEN0_AIA_IMSIC_SHIFT	BIT_ULL(58)
> +#define SMSTATEEN0_AIA_IMSIC		BIT_ULL(SMSTATEEN0_AIA_IMSIC_SHIFT)
> +#define SMSTATEEN0_AIA_SHIFT		BIT_ULL(59)
> +#define SMSTATEEN0_AIA			BIT_ULL(SMSTATEEN0_AIA_SHIFT)
> +#define SMSTATEEN0_AIA_ISEL_SHIFT	BIT_ULL(60)
> +#define SMSTATEEN0_AIA_ISEL		BIT_ULL(SMSTATEEN0_AIA_ISEL_SHIFT)
> +#define SMSTATEEN0_HSENVCFG_SHIFT	BIT_ULL(62)
> +#define SMSTATEEN0_HSENVCFG		BIT_ULL(SMSTATEEN0_HSENVCFG_SHIFT)
> +#define SMSTATEEN0_SSTATEEN0_SHIFT	BIT_ULL(63)
> +#define SMSTATEEN0_SSTATEEN0		BIT_ULL(SMSTATEEN0_SSTATEEN0_SHIFT)
>

Do not wrap _SHIFT values with BIT_ULL(). Likely caused by too aggressive `sed //`.

best,
- Tomasz

>  /* symbolic CSR names: */
>  #define CSR_CYCLE		0xc00
> -- 
> 2.45.2
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] RISC-V: hwprobe: Use BIT macro to avoid warnings
  2025-02-05 20:40 ` [PATCH v2 1/2] RISC-V: hwprobe: Use BIT macro to avoid warnings Palmer Dabbelt
@ 2025-02-06  8:58   ` Andreas Schwab
  0 siblings, 0 replies; 5+ messages in thread
From: Andreas Schwab @ 2025-02-06  8:58 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: linux-riscv, alex, Charlie Jenkins, Mr.Bossman075, Jesse Taube

On Feb 05 2025, Palmer Dabbelt wrote:

> From: Jesse Taube <jesse@rivosinc.com>
>
> In uapi/asm/hwprobe.h file, (1 << N) is used to define the bit field
> which causes checkpatch to warn. Use BIT(N) and BIT_ULL(N) to avoid
> these warnings.

_BITUL(N) and _BITULL(N)

> @@ -98,6 +99,6 @@ struct riscv_hwprobe {
>  /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>  
>  /* Flags */
> -#define RISCV_HWPROBE_WHICH_CPUS	(1 << 0)
> +#define RISCV_HWPROBE_WHICH_CPUS	BIT(0)

s/BIT/_BITUL/

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

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^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-02-06  8:58 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-05 20:40 [PATCH v2 0/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
2025-02-05 20:40 ` [PATCH v2 1/2] RISC-V: hwprobe: Use BIT macro to avoid warnings Palmer Dabbelt
2025-02-06  8:58   ` Andreas Schwab
2025-02-05 20:40 ` [PATCH v2 2/2] RISC-V: Use BIT_ULL(x) instead of 1ULL << x Palmer Dabbelt
2025-02-06  6:15   ` Tomasz Jeznach

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