* [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
@ 2025-11-18 9:52 Shawn Lin
2025-11-18 9:52 ` [PATCH v2 2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562 Shawn Lin
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Shawn Lin @ 2025-11-18 9:52 UTC (permalink / raw)
To: Vinod Koul
Cc: Kishon Vijay Abraham I, Neil Armstrong, Heiko Stuebner, linux-phy,
linux-rockchip, Shawn Lin
When PCIe link enters L1 PM substates, the PHY will turn off its
PLL for power-saving. However, it turns off the PLL too fast which
leads the PHY to be broken. According to the PHY document, we need
to delay PLL turnoff time.
Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2:
- add more commit message
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index a3ef198..e303bec 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -21,6 +21,9 @@
#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
/* RK3528 COMBO PHY REG */
+#define RK3528_PHYREG5 0x14
+#define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3)
+#define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3)
#define RK3528_PHYREG6 0x18
#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
#define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
@@ -504,6 +507,10 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
case REF_CLOCK_100MHz:
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->type == PHY_TYPE_PCIE) {
+ /* Gate_tx_pck_sel length select for L1ss support */
+ rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
+ RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF, RK3528_PHYREG5);
+
/* PLL KVCO tuning fine */
val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562
2025-11-18 9:52 [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528 Shawn Lin
@ 2025-11-18 9:52 ` Shawn Lin
2025-11-18 13:47 ` Neil Armstrong
2025-11-18 13:47 ` [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528 Neil Armstrong
2025-11-20 17:12 ` Vinod Koul
2 siblings, 1 reply; 5+ messages in thread
From: Shawn Lin @ 2025-11-18 9:52 UTC (permalink / raw)
To: Vinod Koul
Cc: Kishon Vijay Abraham I, Neil Armstrong, Heiko Stuebner, linux-phy,
linux-rockchip, Shawn Lin
When PCIe link enters L1 PM substates, the PHY will turn off its
PLL for power-saving. However, it turns off the PLL too fast which
leads the PHY to be broken. According to the PHY document, we need
to delay PLL turnoff time.
Fixes: f13bff25161b ("phy: rockchip-naneng-combo: Support rk3562")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2:
- add more commit message
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index e303bec..7f8fc8e 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -106,6 +106,10 @@
#define RK3568_PHYREG18 0x44
#define RK3568_PHYREG18_PLL_LOOP 0x32
+#define RK3568_PHYREG30 0x74
+#define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7)
+#define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7)
+
#define RK3568_PHYREG32 0x7C
#define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)
#define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
@@ -664,6 +668,10 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
case REF_CLOCK_100MHz:
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->type == PHY_TYPE_PCIE) {
+ /* Gate_tx_pck_sel length select for L1ss support */
+ rockchip_combphy_updatel(priv, RK3568_PHYREG30_GATE_TX_PCK_SEL,
+ RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF,
+ RK3568_PHYREG30);
/* PLL KVCO tuning fine */
val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
RK3568_PHYREG33_PLL_KVCO_VALUE);
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2 2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562
2025-11-18 9:52 ` [PATCH v2 2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562 Shawn Lin
@ 2025-11-18 13:47 ` Neil Armstrong
0 siblings, 0 replies; 5+ messages in thread
From: Neil Armstrong @ 2025-11-18 13:47 UTC (permalink / raw)
To: Shawn Lin, Vinod Koul
Cc: Kishon Vijay Abraham I, Heiko Stuebner, linux-phy, linux-rockchip
On 11/18/25 10:52, Shawn Lin wrote:
> When PCIe link enters L1 PM substates, the PHY will turn off its
> PLL for power-saving. However, it turns off the PLL too fast which
> leads the PHY to be broken. According to the PHY document, we need
> to delay PLL turnoff time.
>
> Fixes: f13bff25161b ("phy: rockchip-naneng-combo: Support rk3562")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> Changes in v2:
> - add more commit message
>
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index e303bec..7f8fc8e 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -106,6 +106,10 @@
> #define RK3568_PHYREG18 0x44
> #define RK3568_PHYREG18_PLL_LOOP 0x32
>
> +#define RK3568_PHYREG30 0x74
> +#define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7)
> +#define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7)
> +
> #define RK3568_PHYREG32 0x7C
> #define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)
> #define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
> @@ -664,6 +668,10 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
> case REF_CLOCK_100MHz:
> rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
> if (priv->type == PHY_TYPE_PCIE) {
> + /* Gate_tx_pck_sel length select for L1ss support */
> + rockchip_combphy_updatel(priv, RK3568_PHYREG30_GATE_TX_PCK_SEL,
> + RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF,
> + RK3568_PHYREG30);
> /* PLL KVCO tuning fine */
> val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> RK3568_PHYREG33_PLL_KVCO_VALUE);
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
2025-11-18 9:52 [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528 Shawn Lin
2025-11-18 9:52 ` [PATCH v2 2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562 Shawn Lin
@ 2025-11-18 13:47 ` Neil Armstrong
2025-11-20 17:12 ` Vinod Koul
2 siblings, 0 replies; 5+ messages in thread
From: Neil Armstrong @ 2025-11-18 13:47 UTC (permalink / raw)
To: Shawn Lin, Vinod Koul
Cc: Kishon Vijay Abraham I, Heiko Stuebner, linux-phy, linux-rockchip
On 11/18/25 10:52, Shawn Lin wrote:
> When PCIe link enters L1 PM substates, the PHY will turn off its
> PLL for power-saving. However, it turns off the PLL too fast which
> leads the PHY to be broken. According to the PHY document, we need
> to delay PLL turnoff time.
>
> Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> Changes in v2:
> - add more commit message
>
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index a3ef198..e303bec 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -21,6 +21,9 @@
> #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
>
> /* RK3528 COMBO PHY REG */
> +#define RK3528_PHYREG5 0x14
> +#define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3)
> +#define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3)
> #define RK3528_PHYREG6 0x18
> #define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
> #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
> @@ -504,6 +507,10 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
> case REF_CLOCK_100MHz:
> rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
> if (priv->type == PHY_TYPE_PCIE) {
> + /* Gate_tx_pck_sel length select for L1ss support */
> + rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
> + RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF, RK3528_PHYREG5);
> +
> /* PLL KVCO tuning fine */
> val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
> rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
Thanks for updating, it's clearer now !
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
2025-11-18 9:52 [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528 Shawn Lin
2025-11-18 9:52 ` [PATCH v2 2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562 Shawn Lin
2025-11-18 13:47 ` [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528 Neil Armstrong
@ 2025-11-20 17:12 ` Vinod Koul
2 siblings, 0 replies; 5+ messages in thread
From: Vinod Koul @ 2025-11-20 17:12 UTC (permalink / raw)
To: Shawn Lin
Cc: Kishon Vijay Abraham I, Neil Armstrong, Heiko Stuebner, linux-phy,
linux-rockchip
On Tue, 18 Nov 2025 17:52:05 +0800, Shawn Lin wrote:
> When PCIe link enters L1 PM substates, the PHY will turn off its
> PLL for power-saving. However, it turns off the PLL too fast which
> leads the PHY to be broken. According to the PHY document, we need
> to delay PLL turnoff time.
>
>
Applied, thanks!
[1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
commit: a2a18e5da64f8da306fa97c397b4c739ea776f37
[2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562
commit: be866e68966d20bcc4a73708093d577176f99c0c
Best regards,
--
~Vinod
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2025-11-18 9:52 [PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528 Shawn Lin
2025-11-18 9:52 ` [PATCH v2 2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562 Shawn Lin
2025-11-18 13:47 ` Neil Armstrong
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