[PATCH] arm64: dts: rockchip: Fix iomux for PCIe on rk3399

[PATCH] arm64: dts: rockchip: Fix iomux for PCIe on rk3399

[Vicente Bergas]

Fix PCIe pins according to the documentation
http://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf
in page 301:
GRF_GPIO2D_IOMUX[5:4] gpio2d2_sel
  0: gpio
  1: sdio_detectn
  2: pcie_clkreqn
and page 313:
GRF_GPIO4D_IOMUX[1:0] gpio4d0_sel
  0: gpio
  1: pcie_clkreqnb

Signed-off-by: Vicente Bergas <vicencb@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index ada724b12..b37dac094 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -2666,13 +2666,11 @@ hdmi_cec: hdmi-cec {
 
 		pcie {
 			pcie_clkreqn_cpm: pci-clkreqn-cpm {
-				rockchip,pins =
-					<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+				rockchip,pins = <2 RK_PD2 2 &pcfg_pull_none>;
 			};
 
 			pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
-				rockchip,pins =
-					<4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+				rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none>;
 			};
 		};
 
-- 
2.29.2


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Re: [PATCH] arm64: dts: rockchip: Fix iomux for PCIe on rk3399

[Robin Murphy]

On 2020-12-01 15:05, Vicente Bergas wrote:
> Fix PCIe pins according to the documentation
> http://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf
> in page 301:
> GRF_GPIO2D_IOMUX[5:4] gpio2d2_sel
>    0: gpio
>    1: sdio_detectn
>    2: pcie_clkreqn
> and page 313:
> GRF_GPIO4D_IOMUX[1:0] gpio4d0_sel
>    0: gpio
>    1: pcie_clkreqnb

What exactly is this fixing? Commit 461a00bb9d53 explicitly removed pin 
configurations for these functions on the grounds that they apparently 
don't work. FWIW it looks like they might also be related to some magic 
in GRF_SOC_CON7 which nobody's touching either.

Robin.

> Signed-off-by: Vicente Bergas <vicencb@gmail.com>
> ---
>   arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++----
>   1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index ada724b12..b37dac094 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -2666,13 +2666,11 @@ hdmi_cec: hdmi-cec {
>   
>   		pcie {
>   			pcie_clkreqn_cpm: pci-clkreqn-cpm {
> -				rockchip,pins =
> -					<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
> +				rockchip,pins = <2 RK_PD2 2 &pcfg_pull_none>;
>   			};
>   
>   			pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
> -				rockchip,pins =
> -					<4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
> +				rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none>;
>   			};
>   		};
>   
> 

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Re: [PATCH] arm64: dts: rockchip: Fix iomux for PCIe on rk3399

[Vicente Bergas]

On Fri, Dec 4, 2020 at 1:01 PM Robin Murphy <robin.murphy@arm.com> wrote:
>
> On 2020-12-01 15:05, Vicente Bergas wrote:
> > Fix PCIe pins according to the documentation
> > http://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf
> > in page 301:
> > GRF_GPIO2D_IOMUX[5:4] gpio2d2_sel
> >    0: gpio
> >    1: sdio_detectn
> >    2: pcie_clkreqn
> > and page 313:
> > GRF_GPIO4D_IOMUX[1:0] gpio4d0_sel
> >    0: gpio
> >    1: pcie_clkreqnb
>
> What exactly is this fixing? Commit 461a00bb9d53 explicitly removed pin
> configurations for these functions on the grounds that they apparently
> don't work. FWIW it looks like they might also be related to some magic
> in GRF_SOC_CON7 which nobody's touching either.
>
> Robin.

This fixes nothing.
I've got a non-working NVMe and while debugging the issue found this
mismatch between the DTS and documentation.
So i fixed it by changing the DTS.
Regarding 461a00bb9d53 it looks like the issue is in the documentation
instead, but there are no (public) errata documents.
The issue with the NVMe i've got was unrelated: controller chip not
correctly soldered.
Now i've tested that NVMe again without this change and it still
works, so, ignore this patch.
Thanks for reviewing.

Regards,
  Vicente.

> > Signed-off-by: Vicente Bergas <vicencb@gmail.com>
> > ---
> >   arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++----
> >   1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > index ada724b12..b37dac094 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > @@ -2666,13 +2666,11 @@ hdmi_cec: hdmi-cec {
> >
> >               pcie {
> >                       pcie_clkreqn_cpm: pci-clkreqn-cpm {
> > -                             rockchip,pins =
> > -                                     <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
> > +                             rockchip,pins = <2 RK_PD2 2 &pcfg_pull_none>;
> >                       };
> >
> >                       pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
> > -                             rockchip,pins =
> > -                                     <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
> > +                             rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none>;
> >                       };
> >               };
> >
> >

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Re: [PATCH] arm64: dts: rockchip: Fix iomux for PCIe on rk3399

[Heiko Stübner]

Am Freitag, 4. Dezember 2020, 13:33:16 CET schrieb Vicente Bergas:
> On Fri, Dec 4, 2020 at 1:01 PM Robin Murphy <robin.murphy@arm.com> wrote:
> >
> > On 2020-12-01 15:05, Vicente Bergas wrote:
> > > Fix PCIe pins according to the documentation
> > > http://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf
> > > in page 301:
> > > GRF_GPIO2D_IOMUX[5:4] gpio2d2_sel
> > >    0: gpio
> > >    1: sdio_detectn
> > >    2: pcie_clkreqn
> > > and page 313:
> > > GRF_GPIO4D_IOMUX[1:0] gpio4d0_sel
> > >    0: gpio
> > >    1: pcie_clkreqnb
> >
> > What exactly is this fixing? Commit 461a00bb9d53 explicitly removed pin
> > configurations for these functions on the grounds that they apparently
> > don't work. FWIW it looks like they might also be related to some magic
> > in GRF_SOC_CON7 which nobody's touching either.
> >
> > Robin.
> 
> This fixes nothing.
> I've got a non-working NVMe and while debugging the issue found this
> mismatch between the DTS and documentation.
> So i fixed it by changing the DTS.
> Regarding 461a00bb9d53 it looks like the issue is in the documentation
> instead, but there are no (public) errata documents.
> The issue with the NVMe i've got was unrelated: controller chip not
> correctly soldered.
> Now i've tested that NVMe again without this change and it still
> works, so, ignore this patch.
> Thanks for reviewing.

thanks for letting us know ;-) 

And also thanks Robin for digging up the history of this.
I was about to ask something similar but hadn't found the time yet
to dig through past pcie changes.


Heiko



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