From: Jon Hunter <jonathanh@nvidia.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Ketan Patil <ketanp@nvidia.com>,
thierry.reding@gmail.com
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH v4 1/4] memory: tegra: Group mc-err related registers
Date: Thu, 18 Dec 2025 16:51:45 +0000 [thread overview]
Message-ID: <1244cf8e-d06c-473d-96a6-2b8e126a45de@nvidia.com> (raw)
In-Reply-To: <c43abae8-c160-4798-9f24-d37af59351fa@kernel.org>
On 18/12/2025 16:17, Krzysztof Kozlowski wrote:
> On 24/11/2025 18:35, Ketan Patil wrote:
>> Group MC error related registers into a struct as they could have soc
>> specific values.
>
> I do not understand the goal. The values already have "soc specific
> values". Your commit msg should explain why you are doing this and based
> on that explanation that's a no. There is no point in doing this.
Krzysztof is correct. We need to state here that Tegra264 has different
register offsets that the existing devices and so in order to add
support for Tegra264 we need to first make this change.
Although in patch 4/4 you add Tegra264, looking at this patch alone the
reviewer has no idea why we are doing this and it just looks like churn.
--
nvpublic
next prev parent reply other threads:[~2025-12-18 16:51 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-24 17:35 [PATCH v4 0/4] memory: tegra: Add MC error logging support for Tegra264 SoC Ketan Patil
2025-11-24 17:35 ` [PATCH v4 1/4] memory: tegra: Group mc-err related registers Ketan Patil
2025-12-18 16:17 ` Krzysztof Kozlowski
2025-12-18 16:51 ` Jon Hunter [this message]
2025-12-19 5:43 ` Ketan Patil
2025-11-24 17:35 ` [PATCH v4 2/4] memory: tegra: Group register and fields Ketan Patil
2025-11-24 17:35 ` [PATCH v4 3/4] memory: tegra: Add support for multiple irqs Ketan Patil
2025-12-18 16:54 ` Jon Hunter
2025-11-24 17:35 ` [PATCH v4 4/4] memory: tegra: Add MC error logging support for Tegra264 Ketan Patil
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