From: Jon Hunter <jonathanh@nvidia.com>
To: Ketan Patil <ketanp@nvidia.com>,
krzk@kernel.org, thierry.reding@gmail.com
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH v4 3/4] memory: tegra: Add support for multiple irqs
Date: Thu, 18 Dec 2025 16:54:30 +0000 [thread overview]
Message-ID: <162cb2d5-6e1b-44dc-8c4a-facdf2f0de5e@nvidia.com> (raw)
In-Reply-To: <20251124173510.2602663-4-ketanp@nvidia.com>
On 24/11/2025 17:35, Ketan Patil wrote:
> Add support to handle multiple MC interrupts lines as the number of
> interrupt lines could vary based upon SoC. Add field to specify the
> number of interrupts and iterate over the number of interrupts to
> register handler for each interrupt. SoC with multiple interrupts
> will be added in subsequent patches.
Same here. We need to be explicit. The 'could vary' sounds like it is
theoretically possible. However, what we need to say is that Tegra264
supports multiple MC interrupt lines and so make the necessary changes
to the Tegra MC driver to support devices with more than one interrupt
line.
Jon
--
nvpublic
next prev parent reply other threads:[~2025-12-18 16:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-24 17:35 [PATCH v4 0/4] memory: tegra: Add MC error logging support for Tegra264 SoC Ketan Patil
2025-11-24 17:35 ` [PATCH v4 1/4] memory: tegra: Group mc-err related registers Ketan Patil
2025-12-18 16:17 ` Krzysztof Kozlowski
2025-12-18 16:51 ` Jon Hunter
2025-12-19 5:43 ` Ketan Patil
2025-11-24 17:35 ` [PATCH v4 2/4] memory: tegra: Group register and fields Ketan Patil
2025-11-24 17:35 ` [PATCH v4 3/4] memory: tegra: Add support for multiple irqs Ketan Patil
2025-12-18 16:54 ` Jon Hunter [this message]
2025-11-24 17:35 ` [PATCH v4 4/4] memory: tegra: Add MC error logging support for Tegra264 Ketan Patil
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