[PATCH 16/22] usb: xhci: relocate all port register macros to xhci-port.h

[Niklas Neronin <niklas.neronin@linux.intel.com>]

Move all port register macros to xhci-port.h and place them next to the
corresponding macros for improved organization and readability.

Rename the macros to PORTSC_*_BITS to better reflect that they describe
bitfields within the PORTSC register rather than the entire port
register.

Remove macro XHCI_PORT_RZ.

Signed-off-by: Niklas Neronin <niklas.neronin@linux.intel.com>
---
 drivers/usb/host/xhci-hub.c  | 35 +----------------------------------
 drivers/usb/host/xhci-port.h | 10 ++++++++++
 drivers/usb/host/xhci.c      |  2 --
 3 files changed, 11 insertions(+), 36 deletions(-)

diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index 09b2ae3deb7b..111db70642b1 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -17,8 +17,6 @@
 #include "xhci.h"
 #include "xhci-trace.h"
 
-#define	PORT_WAKE_BITS	(PORT_WOE | PORT_WDE | PORT_WCE)
-
 /* Default sublink speed attribute of each lane */
 static u32 ssp_cap_default_ssa[] = {
 	0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
@@ -388,37 +386,6 @@ static unsigned int xhci_port_speed(int portsc)
 	return 0;
 }
 
-/*
- * These bits are Read Only (RO) and should be saved and written to the
- * registers: 0, 3, 10:13, 24, 30
- * connect status, over-current status, port speed, and device removable.
- * connect status and port speed are also sticky - meaning they're in
- * the AUX well and they aren't changed by a hot, warm, or cold reset.
- */
-#define	XHCI_PORT_RO	(PORT_CCS | PORT_OCA | PORT_SPEED_MASK | PORT_CAS | PORT_DR)
-/*
- * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
- * bits 5:8, 9, 14:15, 25, 26, 27
- * link state, port power, port indicator state, "wake on" enable state
- */
-#define XHCI_PORT_RWS	(PORT_PLS_MASK | PORT_PP | PORT_PIC_MASK | PORT_WCE | \
-			 PORT_WDE | PORT_WOE)
-/*
- * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
- * bits 4, 31
- */
-#define	XHCI_PORT_RW1S	(PORT_PR | PORT_WPR)
-/*
- * Bit 16 is RW, and writing a '1' to it causes the link state control to be
- * latched in
- */
-#define	XHCI_PORT_RW	(PORT_LWS)
-/*
- * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
- * bits 2, 28:31
- */
-#define	XHCI_PORT_RZ	((1<<2) | (0xf<<28))
-
 /**
  * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable
  * @portsc: u32 port value read from portsc register to be cleanup up
@@ -437,7 +404,7 @@ static unsigned int xhci_port_speed(int portsc)
 u32 xhci_port_state_to_neutral(u32 portsc)
 {
 	/* Save read-only status and port state */
-	return (portsc & XHCI_PORT_RO) | (portsc & XHCI_PORT_RWS);
+	return (portsc & PORTSC_RO_BITS) | (portsc & PORTSC_RWS_BITS);
 }
 EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral);
 
diff --git a/drivers/usb/host/xhci-port.h b/drivers/usb/host/xhci-port.h
index 28dafbd5ff45..7ec67924cace 100644
--- a/drivers/usb/host/xhci-port.h
+++ b/drivers/usb/host/xhci-port.h
@@ -112,14 +112,24 @@
 #define PORT_WDE	BIT(26)
 /* bit 27 - Wake on Over-current Enable */
 #define PORT_WOE	BIT(27)
+#define	PORT_WAKE_BITS	(PORT_WOE | PORT_WDE | PORT_WCE)
 /* bits 29:28 - RsvdZ */
 /* bit 30 - Device Removable, for USB 3.0 roothub emulation */
 #define PORT_DR		BIT(30)
 /* bit 31 - Warm Port Reset, complete when PORT_WRC is '1' */
 #define PORT_WPR	BIT(31)
+/* These bits are read-only, should be saved and written to the registers. */
+#define	PORTSC_RO_BITS		(PORT_CCS | PORT_OCA | PORT_SPEED_MASK | PORT_CAS | PORT_DR)
+/* Writing 0 clears the bit, writing 1 sets the bit. */
+#define PORTSC_RWS_BITS		(PORT_PLS_MASK | PORT_PP | PORT_PIC_MASK | PORT_WCE | \
+				 PORT_WDE | PORT_WOE)
 /* Writing 1 clears the bit, writing 0 sets the bit. */
 #define PORTSC_RW1CS_BITS	(PORT_PED | PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | PORT_PRC | \
 				 PORT_PLC | PORT_CEC)
+/* Writing 1 sets the bit, writing 0 has no effect. */
+#define PORTSC_RW1S_BITS	(PORT_PR | PORT_WPR)
+/* Writing 1 sets the bit, writing 0 clears the bit. */
+#define	PORTSC_RW_BITS		(PORT_LWS)
 
 /* We mark duplicate entries with -1 */
 #define DUPLICATE_ENTRY ((u8)(-1))
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 0374b1b92810..9e4e5c3cd7c2 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -31,8 +31,6 @@
 #define DRIVER_AUTHOR "Sarah Sharp"
 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
 
-#define	PORT_WAKE_BITS	(PORT_WOE | PORT_WDE | PORT_WCE)
-
 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
 static int link_quirk;
 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
-- 
2.50.1