[PATCH 01/22] usb: xhci: replace bit shifts with the BIT() macro in xhci-port.h

[Niklas Neronin <niklas.neronin@linux.intel.com>]

Use the modern approach.

Signed-off-by: Niklas Neronin <niklas.neronin@linux.intel.com>
---
 drivers/usb/host/xhci-port.h | 44 +++++++++++++++++++-----------------
 1 file changed, 23 insertions(+), 21 deletions(-)

diff --git a/drivers/usb/host/xhci-port.h b/drivers/usb/host/xhci-port.h
index 889b5fb0fcd8..45e081a9c510 100644
--- a/drivers/usb/host/xhci-port.h
+++ b/drivers/usb/host/xhci-port.h
@@ -1,15 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 
+#include <linux/bits.h>
+
 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
 /* true: device connected */
-#define PORT_CONNECT	(1 << 0)
+#define PORT_CONNECT	BIT(0)
 /* true: port enabled */
-#define PORT_PE		(1 << 1)
+#define PORT_PE		BIT(1)
 /* bit 2 reserved and zeroed */
 /* true: port has an over-current condition */
-#define PORT_OC		(1 << 3)
+#define PORT_OC		BIT(3)
 /* true: port reset signaling asserted */
-#define PORT_RESET	(1 << 4)
+#define PORT_RESET	BIT(4)
 /* Port Link State - bits 5:8
  * A read gives the current link PM state of the port,
  * a write with Link State Write Strobe set sets the link state.
@@ -30,7 +32,7 @@
 #define XDEV_RESUME	(0xf << 5)
 
 /* true: port has power (see HCC_PPC) */
-#define PORT_POWER	(1 << 9)
+#define PORT_POWER	BIT(9)
 /* bits 10:13 indicate device speed:
  * 0 - undefined speed - port hasn't be initialized by a reset yet
  * 1 - full speed
@@ -66,21 +68,21 @@
 #define PORT_LED_GREEN	(2 << 14)
 #define PORT_LED_MASK	(3 << 14)
 /* Port Link State Write Strobe - set this when changing link state */
-#define PORT_LINK_STROBE	(1 << 16)
+#define PORT_LINK_STROBE	BIT(16)
 /* true: connect status change */
-#define PORT_CSC	(1 << 17)
+#define PORT_CSC	BIT(17)
 /* true: port enable change */
-#define PORT_PEC	(1 << 18)
+#define PORT_PEC	BIT(18)
 /* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
  * into an enabled state, and the device into the default state.  A "warm" reset
  * also resets the link, forcing the device through the link training sequence.
  * SW can also look at the Port Reset register to see when warm reset is done.
  */
-#define PORT_WRC	(1 << 19)
+#define PORT_WRC	BIT(19)
 /* true: over-current change */
-#define PORT_OCC	(1 << 20)
+#define PORT_OCC	BIT(20)
 /* true: reset change - 1 to 0 transition of PORT_RESET */
-#define PORT_RC		(1 << 21)
+#define PORT_RC		BIT(21)
 /* port link status change - set on some port link state transitions:
  *  Transition				Reason
  *  ------------------------------------------------------------------------------
@@ -94,9 +96,9 @@
  *  - U0 to disabled			L1 entry error with USB 2.1 device
  *  - Any state to inactive		Error on USB 3.0 port
  */
-#define PORT_PLC	(1 << 22)
+#define PORT_PLC	BIT(22)
 /* port configure error change - port failed to configure its link partner */
-#define PORT_CEC	(1 << 23)
+#define PORT_CEC	BIT(23)
 #define PORT_CHANGE_MASK	(PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
 				 PORT_RC | PORT_PLC | PORT_CEC)
 
@@ -105,18 +107,18 @@
  * Sx state. Warm port reset should be perfomed to clear this bit and move port
  * to connected state.
  */
-#define PORT_CAS	(1 << 24)
+#define PORT_CAS	BIT(24)
 /* wake on connect (enable) */
-#define PORT_WKCONN_E	(1 << 25)
+#define PORT_WKCONN_E	BIT(25)
 /* wake on disconnect (enable) */
-#define PORT_WKDISC_E	(1 << 26)
+#define PORT_WKDISC_E	BIT(26)
 /* wake on over-current (enable) */
-#define PORT_WKOC_E	(1 << 27)
+#define PORT_WKOC_E	BIT(27)
 /* bits 28:29 reserved */
 /* true: device is non-removable - for USB 3.0 roothub emulation */
-#define PORT_DEV_REMOVE	(1 << 30)
+#define PORT_DEV_REMOVE	BIT(30)
 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
-#define PORT_WR		(1 << 31)
+#define PORT_WR		BIT(31)
 
 /* We mark duplicate entries with -1 */
 #define DUPLICATE_ENTRY ((u8)(-1))
@@ -135,12 +137,12 @@
 /* USB2 Protocol PORTSPMSC */
 #define	PORT_L1S_MASK		7
 #define	PORT_L1S_SUCCESS	1
-#define	PORT_RWE		(1 << 3)
+#define	PORT_RWE		BIT(3)
 #define	PORT_HIRD(p)		(((p) & 0xf) << 4)
 #define	PORT_HIRD_MASK		(0xf << 4)
 #define	PORT_L1DS_MASK		(0xff << 8)
 #define	PORT_L1DS(p)		(((p) & 0xff) << 8)
-#define	PORT_HLE		(1 << 16)
+#define	PORT_HLE		BIT(16)
 #define PORT_TEST_MODE_SHIFT	28
 
 /* USB3 Protocol PORTLI  Port Link Information */
-- 
2.50.1