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From: Amit Machhiwal <amachhiw@linux.ibm.com>
To: Ritesh Harjani <ritesh.list@gmail.com>
Cc: Amit Machhiwal <amachhiw@linux.ibm.com>,
	linuxppc-dev@lists.ozlabs.org,
	Madhavan Srinivasan <maddy@linux.ibm.com>,
	Vaibhav Jain <vaibhav@linux.ibm.com>,
	Harsh Prateek Bora <harshpb@linux.ibm.com>,
	Anushree Mathur <anushree.mathur@linux.ibm.com>,
	Gautam Menghani <gautam@linux.ibm.com>,
	Mukesh Kumar Chaurasiya <mkchauras@gmail.com>,
	Nicholas Piggin <npiggin@gmail.com>,
	Michael Ellerman <mpe@ellerman.id.au>,
	"Christophe Leroy (CS GROUP)" <chleroy@kernel.org>,
	Thomas Huth <thuth@redhat.com>,
	kvm@vger.kernel.org, stable@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3] KVM: PPC: Book3S HV: Validate arch_compat against host compatibility mode
Date: Tue, 16 Jun 2026 19:07:55 +0530	[thread overview]
Message-ID: <20260616190601.49193107-d8-amachhiw@linux.ibm.com> (raw)
In-Reply-To: <8q8eeio8.ritesh.list@gmail.com>

On 2026/06/16 06:39 PM, Ritesh Harjani wrote:
> Amit Machhiwal <amachhiw@linux.ibm.com> writes:
> 
> > On 2026/06/16 05:38 PM, Ritesh Harjani wrote:
> >> Amit Machhiwal <amachhiw@linux.ibm.com> writes:
> >> 
> >> >> > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> >> >> > index 3449dd2b577d..7472b9522f71 100644
> >> >> > --- a/arch/powerpc/include/asm/reg.h
> >> >> > +++ b/arch/powerpc/include/asm/reg.h
> >> >> > @@ -1356,6 +1356,7 @@
> >> >> >  #define PVR_ARCH_300	0x0f000005
> >> >> >  #define PVR_ARCH_31	0x0f000006
> >> >> >  #define PVR_ARCH_31_P11	0x0f000007
> >> >> > +#define PVR_ARCH_INVALID	0xffffffff
> >> >> 
> >> >> Logical processor version is defined as part of the PAPR spec. We should
> >> >> ensure that this invalid PVR is also documented in the PAPR spec.
> >> >> 
> >> >> If you have already taken care of that, then please confirm and feel free to add:
> >> >
> >> > Regarding the PAPR specification documentation: The PAPR spec documents
> >> > the valid Processor Version Register (PVR) values for each processor
> >> > generation (POWER8, POWER9, POWER10, POWER11, etc.). However, the
> >> > PVR_ARCH_INVALID value (0xffffffff) introduced in this patch series is a
> >> > KVM implementation detail used internally to mark invalid compatibility
> >> > mode requests - it's not an architectural value that would be defined in
> >> > PAPR itself.
> >> >
> >> > The validation logic and the use of PVR_ARCH_INVALID as a sentinel value
> >> > are documented in the kernel code and commit message.
> >> >
> >> 
> >> But that still worries me on what if PAPR wants to re-use this value for
> >> some other purpose in future. 
> >
> > This is a valid concern about potential future conflicts with PAPR.
> > However, I'd like to point out that PAPR explicitly specifies:
> >
> >   "The first byte of the logical processor version value shall be 0x0F."
> >
> > Since PVR_ARCH_INVALID (0xffffffff) has a first byte of 0xFF, it's
> > explicitly outside the valid PAPR-defined range for logical PVR values.
> > This means there shouldn't be any risk of future conflict with PAPR
> > specifications.
> >
> 
> aah ok.. That make sense. Thanks for confirming that.
> Can we please update a small comment in the code and log this info,
> maybe something like:

Sure, Ritesh. I can certainly do that in the next version.

Thanks,
Amit.

> 
> /*
>  * PAPR specifies that the first byte of a valid logical PVR value is
>  * 0x0f. 0xffffffff therefore lies permanently outside the PAPR-defined
>  * range and is safe to repurpose as a kernel-internal sentinel. KVM
>  * stores it in vc->arch_compat when userspace requests an unsupported
>  * compatibility mode (e.g. Power11 on a Power10 compat host);
>  * kvmppc_sanity_check() detects this and prevents the vCPU from running
>  * until a valid arch_compat is set.
>  */
> #define PVR_ARCH_INVALID      0xffffffff
> 
> 
> -ritesh
> 


  reply	other threads:[~2026-06-16 13:38 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-09  5:33 [PATCH v3] KVM: PPC: Book3S HV: Validate arch_compat against host compatibility mode Amit Machhiwal
2026-06-16  9:47 ` Ritesh Harjani
2026-06-16 10:54   ` Amit Machhiwal
2026-06-16 12:08     ` Ritesh Harjani
2026-06-16 12:59       ` Amit Machhiwal
2026-06-16 13:09         ` Ritesh Harjani
2026-06-16 13:37           ` Amit Machhiwal [this message]
2026-06-16 10:19 ` Anushree Mathur
2026-06-16 12:22 ` Gautam Menghani

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