From: Segher Boessenkool <segher@kernel.crashing.org>
To: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH] [POWERPC] 85xx: Add basic Uniprocessor MPC8572 DS port
Date: Thu, 13 Sep 2007 18:53:46 +0200 [thread overview]
Message-ID: <5bba19e33a518178eb46f2a1758cff40@kernel.crashing.org> (raw)
In-Reply-To: <A78D5AE1-8578-4971-800E-7209258365F1@kernel.crashing.org>
>> What is a "front side cache"? What exactly does it cache? If it's
>> a cache for one CPU only, that fact should be shown in the device
>> tree somehow.
>
> Its in front of the memory controllers. Its not specific to a given
> CPU.
Ah, I see. That relationship is implicit in the device tree already,
both this cache controller and that memory controller are child nodes
of the same soc node, so your device tree is fine.
Just for my own understanding, is this a coherent cache? (I'm too
lazy to read the manual ;-) )
Segher
next prev parent reply other threads:[~2007-09-13 16:54 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-11 6:29 [PATCH] [POWERPC] 85xx: Add basic Uniprocessor MPC8572 DS port Kumar Gala
2007-09-11 14:17 ` Scott Wood
2007-09-11 15:58 ` Kumar Gala
2007-09-12 13:20 ` Segher Boessenkool
2007-09-13 3:27 ` Kumar Gala
2007-09-13 16:53 ` Segher Boessenkool [this message]
2007-09-13 21:23 ` Kumar Gala
2007-09-11 14:18 ` Olof Johansson
2007-09-11 15:50 ` Kumar Gala
2007-09-11 15:55 ` Olof Johansson
2007-09-11 16:00 ` Kumar Gala
2007-09-11 17:15 ` Olof Johansson
2007-09-11 17:21 ` Scott Wood
2007-09-11 17:33 ` Olof Johansson
2007-09-11 17:48 ` Scott Wood
2007-09-11 17:59 ` Kumar Gala
2007-09-12 3:00 ` David Gibson
2007-09-12 3:35 ` Kumar Gala
2007-09-12 3:37 ` David Gibson
2007-09-12 3:37 ` Olof Johansson
2007-09-12 13:20 ` Segher Boessenkool
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