Re: [PATCH] [POWERPC] 85xx: Add basic Uniprocessor MPC8572 DS port

[Kumar Gala <galak@kernel.crashing.org>]

On Sep 12, 2007, at 8:20 AM, Segher Boessenkool wrote:

>>>> +		l2-cache-controller@20000 {
>>>> +			compatible = "fsl,8572-l2-cache-controller";
>>>> +			reg = <20000 1000>;
>>>> +			cache-line-size = <20>;	// 32 bytes
>>>> +			cache-size = <80000>;	// L2, 512K
>>>> +			interrupt-parent = <&mpic>;
>>>> +			interrupts = <10 2>;
>>>> +		};
>>>
>>> Should this node be referenced by an l2-cache property in the cpu
>>> node?
>>
>> No, its a front side cache.
>
> What is a "front side cache"?  What exactly does it cache?  If it's
> a cache for one CPU only, that fact should be shown in the device
> tree somehow.

Its in front of the memory controllers.  Its not specific to a given  
CPU.

- k