* Re: [PATCH 4/6 v2] powerpc/qe: update QE Serial Number
From: Kumar Gala @ 2009-05-01 22:03 UTC (permalink / raw)
To: Haiying Wang; +Cc: linuxppc-dev
In-Reply-To: <1241206851-27749-2-git-send-email-Haiying.Wang@freescale.com>
On May 1, 2009, at 2:40 PM, Haiying Wang wrote:
> The latest QE chip may have more Serial Number(SNUM)s of thread to
> use. We will
> get the number of SNUMs from device tree by reading the new property
> "fsl,qe-num-snums", and set 28 as the default number of SNUMs so
> that it is
> compatible with the old QE chips' device trees which don't have this
> new
> property. The macro QE_NUM_OF_SNUM is defined as the maximum number
> in QE snum
> table which is 256.
> Also we update the snum_init[] array with 18 more new SNUMs which are
> confirmed to be useful on new chip.
>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> ---
> v2 change: rename the new property as "fsl,qe-num-snums" and move it
> to Required
> section in qe.txt
> .../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 2 +
> arch/powerpc/include/asm/qe.h | 3 +-
> arch/powerpc/sysdev/qe_lib/qe.c | 47 +++++++++++
> +++++++--
> 3 files changed, 47 insertions(+), 5 deletions(-)
applied
- k
^ permalink raw reply
* Re: [PATCH 2/6 v2] powerpc/qe: update risc allocation for QE
From: Kumar Gala @ 2009-05-01 22:03 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev, Haiying Wang
In-Reply-To: <ed82fe3e0905011315j4678d0c4idecc8c66d288367f@mail.gmail.com>
On May 1, 2009, at 3:15 PM, Timur Tabi wrote:
> On Fri, May 1, 2009 at 2:40 PM, Haiying Wang <Haiying.Wang@freescale.com
> > wrote:
>> Change the RISC allocation to macros instead of enum, add function
>> to read the
>> number of risc engines from the new property "fsl,qe-num-riscs"
>> under qe node
>> in dts. Add new property "fsl,qe-num-riscs" description in qe.txt
>>
>> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
>
> Acked-by: Timur Tabi <timur@freescale.com>
Applied to next
- k
^ permalink raw reply
* Re: [PATCH 5/6 v2] net/ucc_geth: Assign six threads to Rx for UEC
From: David Miller @ 2009-05-01 22:03 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev, netdev, Haiying.Wang
In-Reply-To: <F2CB7830-33F9-4F6C-A782-6B086166FC4D@kernel.crashing.org>
From: Kumar Gala <galak@kernel.crashing.org>
Date: Fri, 1 May 2009 16:56:19 -0500
>
> On May 1, 2009, at 2:40 PM, Haiying Wang wrote:
>
>> in the case the QE has 46 SNUMs for the threads to support four UCC
>> Ethernet at
>> 1000Base-T simultaneously.
>>
>> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
>> ---
>> v2 change: Add comments for the Rx threads change.
>> drivers/net/ucc_geth.c | 10 +++++++++-
>> 1 files changed, 9 insertions(+), 1 deletions(-)
>
> Dave,
>
> One more patch for you to Ack and let me handle via the powerpc tree
> because of dependencies.
Acked-by: David S. Miller <davem@davemloft.net>
^ permalink raw reply
* Re: [PATCH 5/6 v2] net/ucc_geth: Assign six threads to Rx for UEC
From: Kumar Gala @ 2009-05-01 21:56 UTC (permalink / raw)
To: David Miller; +Cc: Linuxppc-dev Development, Netdev, Haiying Wang
In-Reply-To: <1241206851-27749-3-git-send-email-Haiying.Wang@freescale.com>
On May 1, 2009, at 2:40 PM, Haiying Wang wrote:
> in the case the QE has 46 SNUMs for the threads to support four UCC
> Ethernet at
> 1000Base-T simultaneously.
>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> ---
> v2 change: Add comments for the Rx threads change.
> drivers/net/ucc_geth.c | 10 +++++++++-
> 1 files changed, 9 insertions(+), 1 deletions(-)
Dave,
One more patch for you to Ack and let me handle via the powerpc tree
because of dependencies.
- k
>
>
> diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
> index 44f8392..1cb2710 100644
> --- a/drivers/net/ucc_geth.c
> +++ b/drivers/net/ucc_geth.c
> @@ -3702,7 +3702,15 @@ static int ucc_geth_probe(struct of_device*
> ofdev, const struct of_device_id *ma
> ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
> ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
> ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
> - ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
> +
> + /* If QE's snum number is 46 which means we need to support
> + * 4 UECs at 1000Base-T simultaneously, we need to allocate
> + * more Threads to Rx.
> + */
> + if (qe_get_num_of_snums() == 46)
> + ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
> + else
> + ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
> }
>
> if (netif_msg_probe(&debug))
> --
> 1.6.0.2
^ permalink raw reply
* Re: [microblaze-uclinux] Re: [PATCH 6/6] Add support for __read_mostly to linux/cache.h
From: Edgar E. Iglesias @ 2009-05-01 21:47 UTC (permalink / raw)
To: Christoph Lameter
Cc: linux-mips, linux-m68k, linux-ia64, linux-sh, Denys Vlasenko,
Greg Ungerer, Heiko Carstens, linuxppc-dev, Paul Mackerras,
H. Peter Anvin, sparclinux, Sam Ravnborg, Thomas Gleixner,
linux-arm-kernel, linux-s390, Jesper Nilsson, linux-am33-list,
Yoshinori Sato, Helge Deller, Ingo Molnar, Geert Uytterhoeven,
Russell King, user-mode-linux-devel, microblaze-uclinux,
Jeff Dike, Jeff Arnold, dev-etrax, Mikael Starvik, Tony Luck,
Cyrill Gorcunov, Michal Simek, Waseem Daher, Richard Henderson,
Chris Zankel, Bryan Wu, linux-m32r, linux-parisc,
Haavard Skinnemoen, Hirokazu Takata, Tim Abbott, Ralf Baechle,
Anders Kaseorg, Kyle McMartin, Paul Mundt, linux-alpha,
Martin Schwidefsky, uclinux-dist-devel, Linus Torvalds,
David S. Miller
In-Reply-To: <alpine.DEB.1.10.0905010948140.18324@qirst.com>
On Fri, May 01, 2009 at 09:52:18AM -0400, Christoph Lameter wrote:
> On Fri, 1 May 2009, Sam Ravnborg wrote:
>
> > Are there any specific reason why we do not support read_mostly on all
> > architectures?
>
> Not that I know of.
>
> > read_mostly is about grouping rarely written data together
> > so what is needed is to introduce this section in the remaining
> > archtectures.
> >
> > Christoph - git log says you did the inital implmentation.
> > Do you agree?
>
> Yes.
>
> There is some concern that __read_mostly is needlessly applied to
> numerous variables that are not used in hot code paths. This may make
> __read_mostly ineffective and actually increase the cache footprint of a
> function since global variables are no longer in the same cacheline. If
> such a function is called and the caches are cold then two cacheline
> fetches have to be done instead of one.
FWIW I think that's a valid concern. Also, I think one can question the
value of __read_mostly for write-through caches, given the mentioned
concern it probably makes things worse for those. IMO there should be
a way to turn it off for arch's that know it's no good for them.
Cheers
^ permalink raw reply
* Re: [PATCH v6] introduce macro spin_event_timeout()
From: Timur Tabi @ 2009-05-01 21:44 UTC (permalink / raw)
To: Sean MacLennan; +Cc: scottwood, linuxppc-dev
In-Reply-To: <20090501173354.64e78def@lappy.seanm.ca>
Sean MacLennan wrote:
> Would cpu_relax be a good thing to put here?
>
> Something like:
>
> while (!(rc = (condition)) && (tb_ticks_since(__start) <= __loops)) \
> if (delay) \
> udelay(delay); \
> else \
> cpu_relax(); \
>
I had that at one point, but then I looked at the code for udelay(), and
it appears that if I do udelay(0), it does something similar to cpu_relax:
start = get_tbl();
while (get_tbl() - start < loops)
HMT_low();
HMT_medium();
cpu_relax does this:
do { HMT_low(); HMT_medium(); barrier(); } while (0)
Well, now that I look at it, cpu_relax() changes the thread priority to
low and then back to medium, whereas udelay() never sets it to low if
'loops' is 0.
I'm okay with changing my code, but I wonder if udelay() should look
like this:
start = get_tbl();
HMT_low();
while (get_tbl() - start < loops)
HMT_low();
HMT_medium();
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [spi-devel-general] [PATCH 9/9] spi_mpc8xxx: s/83xx/8xxx/g
From: Grant Likely @ 2009-05-01 21:42 UTC (permalink / raw)
To: Anton Vorontsov
Cc: David Brownell, linux-kernel, linuxppc-dev, spi-devel-general,
Andrew Morton
In-Reply-To: <20090430234833.GI7901@oksana.dev.rtsoft.ru>
On Thu, Apr 30, 2009 at 5:48 PM, Anton Vorontsov
<avorontsov@ru.mvista.com> wrote:
> Since we renamed the file, we might want to rename the file
> internals too.
>
> Though we don't bother with changing platform driver name and
> platform module alias. The stuff is legacy and hopefully we'll
> remove it soon.
>
I'd say no personally. Its a lot of churn for very little gain. The
filename change alone should be sufficient to clue people into what
the driver is for.
g.
> Suggested-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
> =A0drivers/spi/Kconfig =A0 =A0 =A0 | =A0 =A02 +-
> =A0drivers/spi/Makefile =A0 =A0 =A0| =A0 =A02 +-
> =A0drivers/spi/spi_mpc8xxx.c | =A0396 ++++++++++++++++++++++-------------=
---------
> =A03 files changed, 200 insertions(+), 200 deletions(-)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 3c1845c..9e77bf1 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -139,7 +139,7 @@ config SPI_MPC52xx_PSC
> =A0 =A0 =A0 =A0 =A0This enables using the Freescale MPC52xx Programmable =
Serial
> =A0 =A0 =A0 =A0 =A0Controller in master SPI mode.
>
> -config SPI_MPC83xx
> +config SPI_MPC8xxx
> =A0 =A0 =A0 =A0tristate "Freescale MPC8xxx SPI controller"
> =A0 =A0 =A0 =A0depends on FSL_SOC
> =A0 =A0 =A0 =A0help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index fdc7aa0..18ba6b4 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -24,7 +24,7 @@ obj-$(CONFIG_SPI_OMAP_UWIRE) =A0 =A0 =A0 =A0 =A0+=3D om=
ap_uwire.o
> =A0obj-$(CONFIG_SPI_OMAP24XX) =A0 =A0 =A0 =A0 =A0 =A0 +=3D omap2_mcspi.o
> =A0obj-$(CONFIG_SPI_ORION) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0+=3D orion_spi.o
> =A0obj-$(CONFIG_SPI_MPC52xx_PSC) =A0 =A0 =A0 =A0 =A0+=3D mpc52xx_psc_spi.=
o
> -obj-$(CONFIG_SPI_MPC83xx) =A0 =A0 =A0 =A0 =A0 =A0 =A0+=3D spi_mpc8xxx.o
> +obj-$(CONFIG_SPI_MPC8xxx) =A0 =A0 =A0 =A0 =A0 =A0 =A0+=3D spi_mpc8xxx.o
> =A0obj-$(CONFIG_SPI_S3C24XX_GPIO) =A0 =A0 =A0 =A0 +=3D spi_s3c24xx_gpio.o
> =A0obj-$(CONFIG_SPI_S3C24XX) =A0 =A0 =A0 =A0 =A0 =A0 =A0+=3D spi_s3c24xx.=
o
> =A0obj-$(CONFIG_SPI_TXX9) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 +=3D spi_txx9.o
> diff --git a/drivers/spi/spi_mpc8xxx.c b/drivers/spi/spi_mpc8xxx.c
> index 4192ce4..15d9527 100644
> --- a/drivers/spi/spi_mpc8xxx.c
> +++ b/drivers/spi/spi_mpc8xxx.c
> @@ -1,5 +1,5 @@
> =A0/*
> - * MPC83xx SPI controller driver.
> + * MPC8xxx SPI controller driver.
> =A0*
> =A0* Maintainer: Kumar Gala
> =A0*
> @@ -37,7 +37,7 @@
> =A0#include <asm/irq.h>
>
> =A0/* SPI Controller registers */
> -struct mpc83xx_spi_reg {
> +struct mpc8xxx_spi_reg {
> =A0 =A0 =A0 =A0u8 res1[0x20];
> =A0 =A0 =A0 =A0__be32 mode;
> =A0 =A0 =A0 =A0__be32 event;
> @@ -76,16 +76,16 @@ struct mpc83xx_spi_reg {
> =A0#define =A0 =A0 =A0 =A0SPIM_NF =A0 =A0 =A0 =A0 0x00000100 =A0 =A0 =A0/=
* Not full */
>
> =A0/* SPI Controller driver's private data. */
> -struct mpc83xx_spi {
> - =A0 =A0 =A0 struct mpc83xx_spi_reg __iomem *base;
> +struct mpc8xxx_spi {
> + =A0 =A0 =A0 struct mpc8xxx_spi_reg __iomem *base;
>
> =A0 =A0 =A0 =A0/* rx & tx bufs from the spi_transfer */
> =A0 =A0 =A0 =A0const void *tx;
> =A0 =A0 =A0 =A0void *rx;
>
> =A0 =A0 =A0 =A0/* functions to deal with different sized buffers */
> - =A0 =A0 =A0 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
> - =A0 =A0 =A0 u32(*get_tx) (struct mpc83xx_spi *);
> + =A0 =A0 =A0 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
> + =A0 =A0 =A0 u32(*get_tx) (struct mpc8xxx_spi *);
>
> =A0 =A0 =A0 =A0unsigned int count;
> =A0 =A0 =A0 =A0unsigned int irq;
> @@ -107,44 +107,44 @@ struct mpc83xx_spi {
> =A0 =A0 =A0 =A0struct completion done;
> =A0};
>
> -struct spi_mpc83xx_cs {
> +struct spi_mpc8xxx_cs {
> =A0 =A0 =A0 =A0/* functions to deal with different sized buffers */
> - =A0 =A0 =A0 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
> - =A0 =A0 =A0 u32 (*get_tx) (struct mpc83xx_spi *);
> + =A0 =A0 =A0 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
> + =A0 =A0 =A0 u32 (*get_tx) (struct mpc8xxx_spi *);
> =A0 =A0 =A0 =A0u32 rx_shift; =A0 =A0 =A0 =A0 =A0 /* RX data reg shift whe=
n in qe mode */
> =A0 =A0 =A0 =A0u32 tx_shift; =A0 =A0 =A0 =A0 =A0 /* TX data reg shift whe=
n in qe mode */
> =A0 =A0 =A0 =A0u32 hw_mode; =A0 =A0 =A0 =A0 =A0 =A0/* Holds HW mode regis=
ter settings */
> =A0};
>
> -static inline void mpc83xx_spi_write_reg(__be32 __iomem *reg, u32 val)
> +static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
> =A0{
> =A0 =A0 =A0 =A0out_be32(reg, val);
> =A0}
>
> -static inline u32 mpc83xx_spi_read_reg(__be32 __iomem *reg)
> +static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
> =A0{
> =A0 =A0 =A0 =A0return in_be32(reg);
> =A0}
>
> =A0#define MPC83XX_SPI_RX_BUF(type) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> =A0static =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> -void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi=
) \
> +void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi=
) \
> =A0{ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
\
> - =A0 =A0 =A0 type *rx =3D mpc83xx_spi->rx; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> - =A0 =A0 =A0 *rx++ =3D (type)(data >> mpc83xx_spi->rx_shift); =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
> - =A0 =A0 =A0 mpc83xx_spi->rx =3D rx; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> + =A0 =A0 =A0 type *rx =3D mpc8xxx_spi->rx; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> + =A0 =A0 =A0 *rx++ =3D (type)(data >> mpc8xxx_spi->rx_shift); =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
> + =A0 =A0 =A0 mpc8xxx_spi->rx =3D rx; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> =A0}
>
> =A0#define MPC83XX_SPI_TX_BUF(type) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 \
> =A0static =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> -u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
> +u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
> =A0{ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
> =A0 =A0 =A0 =A0u32 data; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> - =A0 =A0 =A0 const type *tx =3D mpc83xx_spi->tx; =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 \
> + =A0 =A0 =A0 const type *tx =3D mpc8xxx_spi->tx; =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 \
> =A0 =A0 =A0 =A0if (!tx) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return 0; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> - =A0 =A0 =A0 data =3D *tx++ << mpc83xx_spi->tx_shift; =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0\
> - =A0 =A0 =A0 mpc83xx_spi->tx =3D tx; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> + =A0 =A0 =A0 data =3D *tx++ << mpc8xxx_spi->tx_shift; =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0\
> + =A0 =A0 =A0 mpc8xxx_spi->tx =3D tx; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 \
> =A0 =A0 =A0 =A0return data; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\
> =A0}
>
> @@ -155,12 +155,12 @@ MPC83XX_SPI_TX_BUF(u8)
> =A0MPC83XX_SPI_TX_BUF(u16)
> =A0MPC83XX_SPI_TX_BUF(u32)
>
> -static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
> +static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
> =A0{
> - =A0 =A0 =A0 struct mpc83xx_spi *mpc83xx_spi =3D spi_master_get_devdata(=
spi->master);
> + =A0 =A0 =A0 struct mpc8xxx_spi *mpc8xxx_spi =3D spi_master_get_devdata(=
spi->master);
> =A0 =A0 =A0 =A0struct fsl_spi_platform_data *pdata =3D spi->dev.parent->p=
latform_data;
> =A0 =A0 =A0 =A0bool pol =3D spi->mode & SPI_CS_HIGH;
> - =A0 =A0 =A0 struct spi_mpc83xx_cs =A0 *cs =3D spi->controller_state;
> + =A0 =A0 =A0 struct spi_mpc8xxx_cs =A0 *cs =3D spi->controller_state;
>
> =A0 =A0 =A0 =A0if (value =3D=3D BITBANG_CS_INACTIVE) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (pdata->cs_control)
> @@ -168,16 +168,16 @@ static void mpc83xx_spi_chipselect(struct spi_devic=
e *spi, int value)
> =A0 =A0 =A0 =A0}
>
> =A0 =A0 =A0 =A0if (value =3D=3D BITBANG_CS_ACTIVE) {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 u32 regval =3D mpc83xx_spi_read_reg(&mpc83x=
x_spi->base->mode);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 u32 regval =3D mpc8xxx_spi_read_reg(&mpc8xx=
x_spi->base->mode);
>
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi->rx_shift =3D cs->rx_shift;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi->tx_shift =3D cs->tx_shift;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi->get_rx =3D cs->get_rx;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi->get_tx =3D cs->get_tx;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi->rx_shift =3D cs->rx_shift;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi->tx_shift =3D cs->tx_shift;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi->get_rx =3D cs->get_rx;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi->get_tx =3D cs->get_tx;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (cs->hw_mode !=3D regval) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0unsigned long flags;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 __be32 __iomem *mode =3D &m=
pc83xx_spi->base->mode;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 __be32 __iomem *mode =3D &m=
pc8xxx_spi->base->mode;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0regval =3D cs->hw_mode;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Turn off IRQs locally t=
o minimize time that
> @@ -185,8 +185,8 @@ static void mpc83xx_spi_chipselect(struct spi_device =
*spi, int value)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0local_irq_save(flags);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Turn off SPI unit prior=
changing mode */
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi_write_reg(mode,=
regval & ~SPMODE_ENABLE);
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi_write_reg(mode,=
regval);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi_write_reg(mode,=
regval & ~SPMODE_ENABLE);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi_write_reg(mode,=
regval);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0local_irq_restore(flags);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (pdata->cs_control)
> @@ -195,15 +195,15 @@ static void mpc83xx_spi_chipselect(struct spi_devic=
e *spi, int value)
> =A0}
>
> =A0static
> -int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transf=
er *t)
> +int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transf=
er *t)
> =A0{
> - =A0 =A0 =A0 struct mpc83xx_spi *mpc83xx_spi;
> + =A0 =A0 =A0 struct mpc8xxx_spi *mpc8xxx_spi;
> =A0 =A0 =A0 =A0u32 regval;
> =A0 =A0 =A0 =A0u8 bits_per_word, pm;
> =A0 =A0 =A0 =A0u32 hz;
> - =A0 =A0 =A0 struct spi_mpc83xx_cs =A0 *cs =3D spi->controller_state;
> + =A0 =A0 =A0 struct spi_mpc8xxx_cs =A0 *cs =3D spi->controller_state;
>
> - =A0 =A0 =A0 mpc83xx_spi =3D spi_master_get_devdata(spi->master);
> + =A0 =A0 =A0 mpc8xxx_spi =3D spi_master_get_devdata(spi->master);
>
> =A0 =A0 =A0 =A0if (t) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bits_per_word =3D t->bits_per_word;
> @@ -228,26 +228,26 @@ int mpc83xx_spi_setup_transfer(struct spi_device *s=
pi, struct spi_transfer *t)
> =A0 =A0 =A0 =A0cs->rx_shift =3D 0;
> =A0 =A0 =A0 =A0cs->tx_shift =3D 0;
> =A0 =A0 =A0 =A0if (bits_per_word <=3D 8) {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_rx =3D mpc83xx_spi_rx_buf_u8;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_tx =3D mpc83xx_spi_tx_buf_u8;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (mpc83xx_spi->qe_mode) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_rx =3D mpc8xxx_spi_rx_buf_u8;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_tx =3D mpc8xxx_spi_tx_buf_u8;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (mpc8xxx_spi->qe_mode) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->rx_shift =3D 16;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->tx_shift =3D 24;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0} else if (bits_per_word <=3D 16) {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_rx =3D mpc83xx_spi_rx_buf_u16;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_tx =3D mpc83xx_spi_tx_buf_u16;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (mpc83xx_spi->qe_mode) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_rx =3D mpc8xxx_spi_rx_buf_u16;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_tx =3D mpc8xxx_spi_tx_buf_u16;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (mpc8xxx_spi->qe_mode) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->rx_shift =3D 16;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->tx_shift =3D 16;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0} else if (bits_per_word <=3D 32) {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_rx =3D mpc83xx_spi_rx_buf_u32;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_tx =3D mpc83xx_spi_tx_buf_u32;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_rx =3D mpc8xxx_spi_rx_buf_u32;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cs->get_tx =3D mpc8xxx_spi_tx_buf_u32;
> =A0 =A0 =A0 =A0} else
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return -EINVAL;
>
> - =A0 =A0 =A0 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
> + =A0 =A0 =A0 if (mpc8xxx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->tx_shift =3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (bits_per_word <=3D 8)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->rx_shift =3D 8;
> @@ -255,10 +255,10 @@ int mpc83xx_spi_setup_transfer(struct spi_device *s=
pi, struct spi_transfer *t)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->rx_shift =3D 0;
> =A0 =A0 =A0 =A0}
>
> - =A0 =A0 =A0 mpc83xx_spi->rx_shift =3D cs->rx_shift;
> - =A0 =A0 =A0 mpc83xx_spi->tx_shift =3D cs->tx_shift;
> - =A0 =A0 =A0 mpc83xx_spi->get_rx =3D cs->get_rx;
> - =A0 =A0 =A0 mpc83xx_spi->get_tx =3D cs->get_tx;
> + =A0 =A0 =A0 mpc8xxx_spi->rx_shift =3D cs->rx_shift;
> + =A0 =A0 =A0 mpc8xxx_spi->tx_shift =3D cs->tx_shift;
> + =A0 =A0 =A0 mpc8xxx_spi->get_rx =3D cs->get_rx;
> + =A0 =A0 =A0 mpc8xxx_spi->get_tx =3D cs->get_tx;
>
> =A0 =A0 =A0 =A0if (bits_per_word =3D=3D 32)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bits_per_word =3D 0;
> @@ -271,25 +271,25 @@ int mpc83xx_spi_setup_transfer(struct spi_device *s=
pi, struct spi_transfer *t)
>
> =A0 =A0 =A0 =A0cs->hw_mode |=3D SPMODE_LEN(bits_per_word);
>
> - =A0 =A0 =A0 if ((mpc83xx_spi->spibrg / hz) > 64) {
> + =A0 =A0 =A0 if ((mpc8xxx_spi->spibrg / hz) > 64) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->hw_mode |=3D SPMODE_DIV16;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 pm =3D mpc83xx_spi->spibrg / (hz * 64);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 pm =3D mpc8xxx_spi->spibrg / (hz * 64);
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0WARN_ONCE(pm > 16, "%s: Requested speed is=
too low: %d Hz. "
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"Will use %d Hz instea=
d.\n", dev_name(&spi->dev),
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 hz, mpc83xx_spi->spibrg=
/ 1024);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 hz, mpc8xxx_spi->spibrg=
/ 1024);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (pm > 16)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pm =3D 16;
> =A0 =A0 =A0 =A0} else
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 pm =3D mpc83xx_spi->spibrg / (hz * 4);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 pm =3D mpc8xxx_spi->spibrg / (hz * 4);
> =A0 =A0 =A0 =A0if (pm)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pm--;
>
> =A0 =A0 =A0 =A0cs->hw_mode |=3D SPMODE_PM(pm);
> - =A0 =A0 =A0 regval =3D =A0mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode=
);
> + =A0 =A0 =A0 regval =3D =A0mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode=
);
> =A0 =A0 =A0 =A0if (cs->hw_mode !=3D regval) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0unsigned long flags;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 __be32 __iomem *mode =3D &mpc83xx_spi->base=
->mode;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 __be32 __iomem *mode =3D &mpc8xxx_spi->base=
->mode;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0regval =3D cs->hw_mode;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Turn off IRQs locally to minimize time
> @@ -297,22 +297,22 @@ int mpc83xx_spi_setup_transfer(struct spi_device *s=
pi, struct spi_transfer *t)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0local_irq_save(flags);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Turn off SPI unit prior changing mode *=
/
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi_write_reg(mode, regval & ~SPMOD=
E_ENABLE);
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi_write_reg(mode, regval);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi_write_reg(mode, regval & ~SPMOD=
E_ENABLE);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi_write_reg(mode, regval);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0local_irq_restore(flags);
> =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0return 0;
> =A0}
>
> -static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer =
*t)
> +static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer =
*t)
> =A0{
> - =A0 =A0 =A0 struct mpc83xx_spi *mpc83xx_spi;
> + =A0 =A0 =A0 struct mpc8xxx_spi *mpc8xxx_spi;
> =A0 =A0 =A0 =A0u32 word, len, bits_per_word;
>
> - =A0 =A0 =A0 mpc83xx_spi =3D spi_master_get_devdata(spi->master);
> + =A0 =A0 =A0 mpc8xxx_spi =3D spi_master_get_devdata(spi->master);
>
> - =A0 =A0 =A0 mpc83xx_spi->tx =3D t->tx_buf;
> - =A0 =A0 =A0 mpc83xx_spi->rx =3D t->rx_buf;
> + =A0 =A0 =A0 mpc8xxx_spi->tx =3D t->tx_buf;
> + =A0 =A0 =A0 mpc8xxx_spi->rx =3D t->rx_buf;
> =A0 =A0 =A0 =A0bits_per_word =3D spi->bits_per_word;
> =A0 =A0 =A0 =A0if (t->bits_per_word)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bits_per_word =3D t->bits_per_word;
> @@ -329,26 +329,26 @@ static int mpc83xx_spi_bufs(struct spi_device *spi,=
struct spi_transfer *t)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return -EINVAL;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0len /=3D 2;
> =A0 =A0 =A0 =A0}
> - =A0 =A0 =A0 mpc83xx_spi->count =3D len;
> + =A0 =A0 =A0 mpc8xxx_spi->count =3D len;
>
> - =A0 =A0 =A0 INIT_COMPLETION(mpc83xx_spi->done);
> + =A0 =A0 =A0 INIT_COMPLETION(mpc8xxx_spi->done);
>
> =A0 =A0 =A0 =A0/* enable rx ints */
> - =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
> + =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, SPIM_NE);
>
> =A0 =A0 =A0 =A0/* transmit word */
> - =A0 =A0 =A0 word =3D mpc83xx_spi->get_tx(mpc83xx_spi);
> - =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
> + =A0 =A0 =A0 word =3D mpc8xxx_spi->get_tx(mpc8xxx_spi);
> + =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->transmit, word);
>
> - =A0 =A0 =A0 wait_for_completion(&mpc83xx_spi->done);
> + =A0 =A0 =A0 wait_for_completion(&mpc8xxx_spi->done);
>
> =A0 =A0 =A0 =A0/* disable rx ints */
> - =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
> + =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
>
> - =A0 =A0 =A0 return mpc83xx_spi->count;
> + =A0 =A0 =A0 return mpc8xxx_spi->count;
> =A0}
>
> -static void mpc83xx_spi_do_one_msg(struct spi_message *m)
> +static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
> =A0{
> =A0 =A0 =A0 =A0struct spi_device *spi =3D m->spi;
> =A0 =A0 =A0 =A0struct spi_transfer *t;
> @@ -364,18 +364,18 @@ static void mpc83xx_spi_do_one_msg(struct spi_messa=
ge *m)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0status =3D -EINVAL;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (cs_change)
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 status =3D =
mpc83xx_spi_setup_transfer(spi, t);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 status =3D =
mpc8xxx_spi_setup_transfer(spi, t);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (status < 0)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (cs_change) {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi_chipselect(spi,=
BITBANG_CS_ACTIVE);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi_chipselect(spi,=
BITBANG_CS_ACTIVE);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ndelay(nsecs);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs_change =3D t->cs_change;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (t->len)
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 status =3D mpc83xx_spi_bufs=
(spi, t);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 status =3D mpc8xxx_spi_bufs=
(spi, t);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (status) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0status =3D -EMSGSIZE;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0break;
> @@ -387,7 +387,7 @@ static void mpc83xx_spi_do_one_msg(struct spi_message=
*m)
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (cs_change) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ndelay(nsecs);
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi_chipselect(spi,=
BITBANG_CS_INACTIVE);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi_chipselect(spi,=
BITBANG_CS_INACTIVE);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ndelay(nsecs);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0}
> @@ -397,42 +397,42 @@ static void mpc83xx_spi_do_one_msg(struct spi_messa=
ge *m)
>
> =A0 =A0 =A0 =A0if (status || !cs_change) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ndelay(nsecs);
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi_chipselect(spi, BITBANG_CS_INAC=
TIVE);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INAC=
TIVE);
> =A0 =A0 =A0 =A0}
>
> - =A0 =A0 =A0 mpc83xx_spi_setup_transfer(spi, NULL);
> + =A0 =A0 =A0 mpc8xxx_spi_setup_transfer(spi, NULL);
> =A0}
>
> -static void mpc83xx_spi_work(struct work_struct *work)
> +static void mpc8xxx_spi_work(struct work_struct *work)
> =A0{
> - =A0 =A0 =A0 struct mpc83xx_spi *mpc83xx_spi =3D container_of(work, stru=
ct mpc83xx_spi,
> + =A0 =A0 =A0 struct mpc8xxx_spi *mpc8xxx_spi =3D container_of(work, stru=
ct mpc8xxx_spi,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 work);
>
> - =A0 =A0 =A0 spin_lock_irq(&mpc83xx_spi->lock);
> - =A0 =A0 =A0 while (!list_empty(&mpc83xx_spi->queue)) {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 struct spi_message *m =3D container_of(mpc8=
3xx_spi->queue.next,
> + =A0 =A0 =A0 spin_lock_irq(&mpc8xxx_spi->lock);
> + =A0 =A0 =A0 while (!list_empty(&mpc8xxx_spi->queue)) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 struct spi_message *m =3D container_of(mpc8=
xxx_spi->queue.next,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 struct spi_message, queue);
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0list_del_init(&m->queue);
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 spin_unlock_irq(&mpc83xx_spi->lock);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 spin_unlock_irq(&mpc8xxx_spi->lock);
>
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi_do_one_msg(m);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi_do_one_msg(m);
>
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 spin_lock_irq(&mpc83xx_spi->lock);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 spin_lock_irq(&mpc8xxx_spi->lock);
> =A0 =A0 =A0 =A0}
> - =A0 =A0 =A0 spin_unlock_irq(&mpc83xx_spi->lock);
> + =A0 =A0 =A0 spin_unlock_irq(&mpc8xxx_spi->lock);
> =A0}
>
> =A0/* the spi->mode bits understood by this driver: */
> =A0#define MODEBITS =A0 =A0 =A0 (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| SPI_LSB_FIRST | SPI_LOOP=
)
>
> -static int mpc83xx_spi_setup(struct spi_device *spi)
> +static int mpc8xxx_spi_setup(struct spi_device *spi)
> =A0{
> - =A0 =A0 =A0 struct mpc83xx_spi *mpc83xx_spi;
> + =A0 =A0 =A0 struct mpc8xxx_spi *mpc8xxx_spi;
> =A0 =A0 =A0 =A0int retval;
> =A0 =A0 =A0 =A0u32 hw_mode;
> - =A0 =A0 =A0 struct spi_mpc83xx_cs =A0 *cs =3D spi->controller_state;
> + =A0 =A0 =A0 struct spi_mpc8xxx_cs =A0 *cs =3D spi->controller_state;
>
> =A0 =A0 =A0 =A0if (spi->mode & ~MODEBITS) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dev_dbg(&spi->dev, "setup: unsupported mod=
e bits %x\n",
> @@ -449,13 +449,13 @@ static int mpc83xx_spi_setup(struct spi_device *spi=
)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return -ENOMEM;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0spi->controller_state =3D cs;
> =A0 =A0 =A0 =A0}
> - =A0 =A0 =A0 mpc83xx_spi =3D spi_master_get_devdata(spi->master);
> + =A0 =A0 =A0 mpc8xxx_spi =3D spi_master_get_devdata(spi->master);
>
> =A0 =A0 =A0 =A0if (!spi->bits_per_word)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0spi->bits_per_word =3D 8;
>
> =A0 =A0 =A0 =A0hw_mode =3D cs->hw_mode; /* Save orginal settings */
> - =A0 =A0 =A0 cs->hw_mode =3D mpc83xx_spi_read_reg(&mpc83xx_spi->base->mo=
de);
> + =A0 =A0 =A0 cs->hw_mode =3D mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mo=
de);
> =A0 =A0 =A0 =A0/* mask out bits we are going to set */
> =A0 =A0 =A0 =A0cs->hw_mode &=3D ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INA=
CTIVEHIGH
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | SPMODE_REV | SPMODE_LOO=
P);
> @@ -469,7 +469,7 @@ static int mpc83xx_spi_setup(struct spi_device *spi)
> =A0 =A0 =A0 =A0if (spi->mode & SPI_LOOP)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->hw_mode |=3D SPMODE_LOOP;
>
> - =A0 =A0 =A0 retval =3D mpc83xx_spi_setup_transfer(spi, NULL);
> + =A0 =A0 =A0 retval =3D mpc8xxx_spi_setup_transfer(spi, NULL);
> =A0 =A0 =A0 =A0if (retval < 0) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cs->hw_mode =3D hw_mode; /* Restore settin=
gs */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return retval;
> @@ -481,21 +481,21 @@ static int mpc83xx_spi_setup(struct spi_device *spi=
)
> =A0 =A0 =A0 =A0return 0;
> =A0}
>
> -static irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
> +static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
> =A0{
> - =A0 =A0 =A0 struct mpc83xx_spi *mpc83xx_spi =3D context_data;
> + =A0 =A0 =A0 struct mpc8xxx_spi *mpc8xxx_spi =3D context_data;
> =A0 =A0 =A0 =A0u32 event;
> =A0 =A0 =A0 =A0irqreturn_t ret =3D IRQ_NONE;
>
> =A0 =A0 =A0 =A0/* Get interrupt events(tx/rx) */
> - =A0 =A0 =A0 event =3D mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
> + =A0 =A0 =A0 event =3D mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->event);
>
> =A0 =A0 =A0 =A0/* We need handle RX first */
> =A0 =A0 =A0 =A0if (event & SPIE_NE) {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 u32 rx_data =3D mpc83xx_spi_read_reg(&mpc83=
xx_spi->base->receive);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 u32 rx_data =3D mpc8xxx_spi_read_reg(&mpc8x=
xx_spi->base->receive);
>
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (mpc83xx_spi->rx)
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi->get_rx(rx_data=
, mpc83xx_spi);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (mpc8xxx_spi->rx)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi->get_rx(rx_data=
, mpc8xxx_spi);
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ret =3D IRQ_HANDLED;
> =A0 =A0 =A0 =A0}
> @@ -503,56 +503,56 @@ static irqreturn_t mpc83xx_spi_irq(s32 irq, void *c=
ontext_data)
> =A0 =A0 =A0 =A0if ((event & SPIE_NF) =3D=3D 0)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* spin until TX is done */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0while (((event =3D
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0mpc83xx_spi_read_reg(&mp=
c83xx_spi->base->event)) &
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0mpc8xxx_spi_read_reg(&mp=
c8xxx_spi->base->event)) &
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0SPIE_NF) =3D=3D 0)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cpu_relax();
>
> - =A0 =A0 =A0 mpc83xx_spi->count -=3D 1;
> - =A0 =A0 =A0 if (mpc83xx_spi->count) {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 u32 word =3D mpc83xx_spi->get_tx(mpc83xx_sp=
i);
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->t=
ransmit, word);
> + =A0 =A0 =A0 mpc8xxx_spi->count -=3D 1;
> + =A0 =A0 =A0 if (mpc8xxx_spi->count) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 u32 word =3D mpc8xxx_spi->get_tx(mpc8xxx_sp=
i);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->t=
ransmit, word);
> =A0 =A0 =A0 =A0} else {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 complete(&mpc83xx_spi->done);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 complete(&mpc8xxx_spi->done);
> =A0 =A0 =A0 =A0}
>
> =A0 =A0 =A0 =A0/* Clear the events */
> - =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
> + =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, event);
>
> =A0 =A0 =A0 =A0return ret;
> =A0}
> -static int mpc83xx_spi_transfer(struct spi_device *spi,
> +static int mpc8xxx_spi_transfer(struct spi_device *spi,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0struct spi=
_message *m)
> =A0{
> - =A0 =A0 =A0 struct mpc83xx_spi *mpc83xx_spi =3D spi_master_get_devdata(=
spi->master);
> + =A0 =A0 =A0 struct mpc8xxx_spi *mpc8xxx_spi =3D spi_master_get_devdata(=
spi->master);
> =A0 =A0 =A0 =A0unsigned long flags;
>
> =A0 =A0 =A0 =A0m->actual_length =3D 0;
> =A0 =A0 =A0 =A0m->status =3D -EINPROGRESS;
>
> - =A0 =A0 =A0 spin_lock_irqsave(&mpc83xx_spi->lock, flags);
> - =A0 =A0 =A0 list_add_tail(&m->queue, &mpc83xx_spi->queue);
> - =A0 =A0 =A0 queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
> - =A0 =A0 =A0 spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
> + =A0 =A0 =A0 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
> + =A0 =A0 =A0 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
> + =A0 =A0 =A0 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
> + =A0 =A0 =A0 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
>
> =A0 =A0 =A0 =A0return 0;
> =A0}
>
>
> -static void mpc83xx_spi_cleanup(struct spi_device *spi)
> +static void mpc8xxx_spi_cleanup(struct spi_device *spi)
> =A0{
> =A0 =A0 =A0 =A0kfree(spi->controller_state);
> =A0}
>
> =A0static struct spi_master * __devinit
> -mpc83xx_spi_probe(struct device *dev, struct resource *mem, unsigned int=
irq)
> +mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int=
irq)
> =A0{
> =A0 =A0 =A0 =A0struct fsl_spi_platform_data *pdata =3D dev->platform_data=
;
> =A0 =A0 =A0 =A0struct spi_master *master;
> - =A0 =A0 =A0 struct mpc83xx_spi *mpc83xx_spi;
> + =A0 =A0 =A0 struct mpc8xxx_spi *mpc8xxx_spi;
> =A0 =A0 =A0 =A0u32 regval;
> =A0 =A0 =A0 =A0int ret =3D 0;
>
> - =A0 =A0 =A0 master =3D spi_alloc_master(dev, sizeof(struct mpc83xx_spi)=
);
> + =A0 =A0 =A0 master =3D spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)=
);
> =A0 =A0 =A0 =A0if (master =3D=3D NULL) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ret =3D -ENOMEM;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goto err;
> @@ -560,36 +560,36 @@ mpc83xx_spi_probe(struct device *dev, struct resour=
ce *mem, unsigned int irq)
>
> =A0 =A0 =A0 =A0dev_set_drvdata(dev, master);
>
> - =A0 =A0 =A0 master->setup =3D mpc83xx_spi_setup;
> - =A0 =A0 =A0 master->transfer =3D mpc83xx_spi_transfer;
> - =A0 =A0 =A0 master->cleanup =3D mpc83xx_spi_cleanup;
> -
> - =A0 =A0 =A0 mpc83xx_spi =3D spi_master_get_devdata(master);
> - =A0 =A0 =A0 mpc83xx_spi->qe_mode =3D pdata->qe_mode;
> - =A0 =A0 =A0 mpc83xx_spi->get_rx =3D mpc83xx_spi_rx_buf_u8;
> - =A0 =A0 =A0 mpc83xx_spi->get_tx =3D mpc83xx_spi_tx_buf_u8;
> - =A0 =A0 =A0 mpc83xx_spi->spibrg =3D pdata->sysclk;
> -
> - =A0 =A0 =A0 mpc83xx_spi->rx_shift =3D 0;
> - =A0 =A0 =A0 mpc83xx_spi->tx_shift =3D 0;
> - =A0 =A0 =A0 if (mpc83xx_spi->qe_mode) {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi->rx_shift =3D 16;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc83xx_spi->tx_shift =3D 24;
> + =A0 =A0 =A0 master->setup =3D mpc8xxx_spi_setup;
> + =A0 =A0 =A0 master->transfer =3D mpc8xxx_spi_transfer;
> + =A0 =A0 =A0 master->cleanup =3D mpc8xxx_spi_cleanup;
> +
> + =A0 =A0 =A0 mpc8xxx_spi =3D spi_master_get_devdata(master);
> + =A0 =A0 =A0 mpc8xxx_spi->qe_mode =3D pdata->qe_mode;
> + =A0 =A0 =A0 mpc8xxx_spi->get_rx =3D mpc8xxx_spi_rx_buf_u8;
> + =A0 =A0 =A0 mpc8xxx_spi->get_tx =3D mpc8xxx_spi_tx_buf_u8;
> + =A0 =A0 =A0 mpc8xxx_spi->spibrg =3D pdata->sysclk;
> +
> + =A0 =A0 =A0 mpc8xxx_spi->rx_shift =3D 0;
> + =A0 =A0 =A0 mpc8xxx_spi->tx_shift =3D 0;
> + =A0 =A0 =A0 if (mpc8xxx_spi->qe_mode) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi->rx_shift =3D 16;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc8xxx_spi->tx_shift =3D 24;
> =A0 =A0 =A0 =A0}
>
> - =A0 =A0 =A0 init_completion(&mpc83xx_spi->done);
> + =A0 =A0 =A0 init_completion(&mpc8xxx_spi->done);
>
> - =A0 =A0 =A0 mpc83xx_spi->base =3D ioremap(mem->start, mem->end - mem->s=
tart + 1);
> - =A0 =A0 =A0 if (mpc83xx_spi->base =3D=3D NULL) {
> + =A0 =A0 =A0 mpc8xxx_spi->base =3D ioremap(mem->start, mem->end - mem->s=
tart + 1);
> + =A0 =A0 =A0 if (mpc8xxx_spi->base =3D=3D NULL) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ret =3D -ENOMEM;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goto put_master;
> =A0 =A0 =A0 =A0}
>
> - =A0 =A0 =A0 mpc83xx_spi->irq =3D irq;
> + =A0 =A0 =A0 mpc8xxx_spi->irq =3D irq;
>
> =A0 =A0 =A0 =A0/* Register for SPI Interrupt */
> - =A0 =A0 =A0 ret =3D request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0, "mpc83xx_spi", mpc83=
xx_spi);
> + =A0 =A0 =A0 ret =3D request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0, "mpc8xxx_spi", mpc8x=
xx_spi);
>
> =A0 =A0 =A0 =A0if (ret !=3D 0)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goto unmap_io;
> @@ -598,25 +598,25 @@ mpc83xx_spi_probe(struct device *dev, struct resour=
ce *mem, unsigned int irq)
> =A0 =A0 =A0 =A0master->num_chipselect =3D pdata->max_chipselect;
>
> =A0 =A0 =A0 =A0/* SPI controller initializations */
> - =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
> - =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
> - =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
> - =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff=
);
> + =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
> + =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
> + =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
> + =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff=
);
>
> =A0 =A0 =A0 =A0/* Enable SPI interface */
> =A0 =A0 =A0 =A0regval =3D pdata->initial_spmode | SPMODE_INIT_VAL | SPMOD=
E_ENABLE;
> =A0 =A0 =A0 =A0if (pdata->qe_mode)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0regval |=3D SPMODE_OP;
>
> - =A0 =A0 =A0 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
> - =A0 =A0 =A0 spin_lock_init(&mpc83xx_spi->lock);
> - =A0 =A0 =A0 init_completion(&mpc83xx_spi->done);
> - =A0 =A0 =A0 INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
> - =A0 =A0 =A0 INIT_LIST_HEAD(&mpc83xx_spi->queue);
> + =A0 =A0 =A0 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
> + =A0 =A0 =A0 spin_lock_init(&mpc8xxx_spi->lock);
> + =A0 =A0 =A0 init_completion(&mpc8xxx_spi->done);
> + =A0 =A0 =A0 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
> + =A0 =A0 =A0 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
>
> - =A0 =A0 =A0 mpc83xx_spi->workqueue =3D create_singlethread_workqueue(
> + =A0 =A0 =A0 mpc8xxx_spi->workqueue =3D create_singlethread_workqueue(
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dev_name(master->dev.parent));
> - =A0 =A0 =A0 if (mpc83xx_spi->workqueue =3D=3D NULL) {
> + =A0 =A0 =A0 if (mpc8xxx_spi->workqueue =3D=3D NULL) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ret =3D -EBUSY;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goto free_irq;
> =A0 =A0 =A0 =A0}
> @@ -626,57 +626,57 @@ mpc83xx_spi_probe(struct device *dev, struct resour=
ce *mem, unsigned int irq)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goto unreg_master;
>
> =A0 =A0 =A0 =A0printk(KERN_INFO
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0"%s: MPC83xx SPI Controller driver at 0x%p (=
irq =3D %d)\n",
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0dev_name(dev), mpc83xx_spi->base, mpc83xx_sp=
i->irq);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0"%s: MPC8xxx SPI Controller driver at 0x%p (=
irq =3D %d)\n",
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0dev_name(dev), mpc8xxx_spi->base, mpc8xxx_sp=
i->irq);
>
> =A0 =A0 =A0 =A0return master;
>
> =A0unreg_master:
> - =A0 =A0 =A0 destroy_workqueue(mpc83xx_spi->workqueue);
> + =A0 =A0 =A0 destroy_workqueue(mpc8xxx_spi->workqueue);
> =A0free_irq:
> - =A0 =A0 =A0 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
> + =A0 =A0 =A0 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
> =A0unmap_io:
> - =A0 =A0 =A0 iounmap(mpc83xx_spi->base);
> + =A0 =A0 =A0 iounmap(mpc8xxx_spi->base);
> =A0put_master:
> =A0 =A0 =A0 =A0spi_master_put(master);
> =A0err:
> =A0 =A0 =A0 =A0return ERR_PTR(ret);
> =A0}
>
> -static int __devexit mpc83xx_spi_remove(struct device *dev)
> +static int __devexit mpc8xxx_spi_remove(struct device *dev)
> =A0{
> - =A0 =A0 =A0 struct mpc83xx_spi *mpc83xx_spi;
> + =A0 =A0 =A0 struct mpc8xxx_spi *mpc8xxx_spi;
> =A0 =A0 =A0 =A0struct spi_master *master;
>
> =A0 =A0 =A0 =A0master =3D dev_get_drvdata(dev);
> - =A0 =A0 =A0 mpc83xx_spi =3D spi_master_get_devdata(master);
> + =A0 =A0 =A0 mpc8xxx_spi =3D spi_master_get_devdata(master);
>
> - =A0 =A0 =A0 flush_workqueue(mpc83xx_spi->workqueue);
> - =A0 =A0 =A0 destroy_workqueue(mpc83xx_spi->workqueue);
> + =A0 =A0 =A0 flush_workqueue(mpc8xxx_spi->workqueue);
> + =A0 =A0 =A0 destroy_workqueue(mpc8xxx_spi->workqueue);
> =A0 =A0 =A0 =A0spi_unregister_master(master);
>
> - =A0 =A0 =A0 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
> - =A0 =A0 =A0 iounmap(mpc83xx_spi->base);
> + =A0 =A0 =A0 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
> + =A0 =A0 =A0 iounmap(mpc8xxx_spi->base);
>
> =A0 =A0 =A0 =A0return 0;
> =A0}
>
> -struct mpc83xx_spi_probe_info {
> +struct mpc8xxx_spi_probe_info {
> =A0 =A0 =A0 =A0struct fsl_spi_platform_data pdata;
> =A0 =A0 =A0 =A0int *gpios;
> =A0 =A0 =A0 =A0bool *alow_flags;
> =A0};
>
> -static struct mpc83xx_spi_probe_info *
> +static struct mpc8xxx_spi_probe_info *
> =A0to_of_pinfo(struct fsl_spi_platform_data *pdata)
> =A0{
> - =A0 =A0 =A0 return container_of(pdata, struct mpc83xx_spi_probe_info, p=
data);
> + =A0 =A0 =A0 return container_of(pdata, struct mpc8xxx_spi_probe_info, p=
data);
> =A0}
>
> -static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on)
> +static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
> =A0{
> =A0 =A0 =A0 =A0struct device *dev =3D spi->dev.parent;
> - =A0 =A0 =A0 struct mpc83xx_spi_probe_info *pinfo =3D to_of_pinfo(dev->p=
latform_data);
> + =A0 =A0 =A0 struct mpc8xxx_spi_probe_info *pinfo =3D to_of_pinfo(dev->p=
latform_data);
> =A0 =A0 =A0 =A0u16 cs =3D spi->chip_select;
> =A0 =A0 =A0 =A0int gpio =3D pinfo->gpios[cs];
> =A0 =A0 =A0 =A0bool alow =3D pinfo->alow_flags[cs];
> @@ -684,11 +684,11 @@ static void mpc83xx_spi_cs_control(struct spi_devic=
e *spi, bool on)
> =A0 =A0 =A0 =A0gpio_set_value(gpio, on ^ alow);
> =A0}
>
> -static int of_mpc83xx_spi_get_chipselects(struct device *dev)
> +static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
> =A0{
> =A0 =A0 =A0 =A0struct device_node *np =3D dev_archdata_get_node(&dev->arc=
hdata);
> =A0 =A0 =A0 =A0struct fsl_spi_platform_data *pdata =3D dev->platform_data=
;
> - =A0 =A0 =A0 struct mpc83xx_spi_probe_info *pinfo =3D to_of_pinfo(pdata)=
;
> + =A0 =A0 =A0 struct mpc8xxx_spi_probe_info *pinfo =3D to_of_pinfo(pdata)=
;
> =A0 =A0 =A0 =A0unsigned int ngpios;
> =A0 =A0 =A0 =A0int i =3D 0;
> =A0 =A0 =A0 =A0int ret;
> @@ -744,7 +744,7 @@ static int of_mpc83xx_spi_get_chipselects(struct devi=
ce *dev)
> =A0 =A0 =A0 =A0}
>
> =A0 =A0 =A0 =A0pdata->max_chipselect =3D ngpios;
> - =A0 =A0 =A0 pdata->cs_control =3D mpc83xx_spi_cs_control;
> + =A0 =A0 =A0 pdata->cs_control =3D mpc8xxx_spi_cs_control;
>
> =A0 =A0 =A0 =A0return 0;
>
> @@ -763,10 +763,10 @@ err_alloc_flags:
> =A0 =A0 =A0 =A0return ret;
> =A0}
>
> -static int of_mpc83xx_spi_free_chipselects(struct device *dev)
> +static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
> =A0{
> =A0 =A0 =A0 =A0struct fsl_spi_platform_data *pdata =3D dev->platform_data=
;
> - =A0 =A0 =A0 struct mpc83xx_spi_probe_info *pinfo =3D to_of_pinfo(pdata)=
;
> + =A0 =A0 =A0 struct mpc8xxx_spi_probe_info *pinfo =3D to_of_pinfo(pdata)=
;
> =A0 =A0 =A0 =A0int i;
>
> =A0 =A0 =A0 =A0if (!pinfo->gpios)
> @@ -782,12 +782,12 @@ static int of_mpc83xx_spi_free_chipselects(struct d=
evice *dev)
> =A0 =A0 =A0 =A0return 0;
> =A0}
>
> -static int __devinit of_mpc83xx_spi_probe(struct of_device *ofdev,
> +static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0const struct of_device_id *ofid)
> =A0{
> =A0 =A0 =A0 =A0struct device *dev =3D &ofdev->dev;
> =A0 =A0 =A0 =A0struct device_node *np =3D ofdev->node;
> - =A0 =A0 =A0 struct mpc83xx_spi_probe_info *pinfo;
> + =A0 =A0 =A0 struct mpc8xxx_spi_probe_info *pinfo;
> =A0 =A0 =A0 =A0struct fsl_spi_platform_data *pdata;
> =A0 =A0 =A0 =A0struct spi_master *master;
> =A0 =A0 =A0 =A0struct resource mem;
> @@ -819,7 +819,7 @@ static int __devinit of_mpc83xx_spi_probe(struct of_d=
evice *ofdev,
> =A0 =A0 =A0 =A0if (prop && !strcmp(prop, "cpu-qe"))
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pdata->qe_mode =3D 1;
>
> - =A0 =A0 =A0 ret =3D of_mpc83xx_spi_get_chipselects(dev);
> + =A0 =A0 =A0 ret =3D of_mpc8xxx_spi_get_chipselects(dev);
> =A0 =A0 =A0 =A0if (ret)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goto err;
>
> @@ -833,7 +833,7 @@ static int __devinit of_mpc83xx_spi_probe(struct of_d=
evice *ofdev,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goto err;
> =A0 =A0 =A0 =A0}
>
> - =A0 =A0 =A0 master =3D mpc83xx_spi_probe(dev, &mem, irq.start);
> + =A0 =A0 =A0 master =3D mpc8xxx_spi_probe(dev, &mem, irq.start);
> =A0 =A0 =A0 =A0if (IS_ERR(master)) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ret =3D PTR_ERR(master);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goto err;
> @@ -844,34 +844,34 @@ static int __devinit of_mpc83xx_spi_probe(struct of=
_device *ofdev,
> =A0 =A0 =A0 =A0return 0;
>
> =A0err:
> - =A0 =A0 =A0 of_mpc83xx_spi_free_chipselects(dev);
> + =A0 =A0 =A0 of_mpc8xxx_spi_free_chipselects(dev);
> =A0err_clk:
> =A0 =A0 =A0 =A0kfree(pinfo);
> =A0 =A0 =A0 =A0return ret;
> =A0}
>
> -static int __devexit of_mpc83xx_spi_remove(struct of_device *ofdev)
> +static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
> =A0{
> =A0 =A0 =A0 =A0int ret;
>
> - =A0 =A0 =A0 ret =3D mpc83xx_spi_remove(&ofdev->dev);
> + =A0 =A0 =A0 ret =3D mpc8xxx_spi_remove(&ofdev->dev);
> =A0 =A0 =A0 =A0if (ret)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return ret;
> - =A0 =A0 =A0 of_mpc83xx_spi_free_chipselects(&ofdev->dev);
> + =A0 =A0 =A0 of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
> =A0 =A0 =A0 =A0return 0;
> =A0}
>
> -static const struct of_device_id of_mpc83xx_spi_match[] =3D {
> +static const struct of_device_id of_mpc8xxx_spi_match[] =3D {
> =A0 =A0 =A0 =A0{ .compatible =3D "fsl,spi" },
> =A0 =A0 =A0 =A0{},
> =A0};
> -MODULE_DEVICE_TABLE(of, of_mpc83xx_spi_match);
> +MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
>
> -static struct of_platform_driver of_mpc83xx_spi_driver =3D {
> - =A0 =A0 =A0 .name =A0 =A0 =A0 =A0 =A0 =3D "mpc83xx_spi",
> - =A0 =A0 =A0 .match_table =A0 =A0=3D of_mpc83xx_spi_match,
> - =A0 =A0 =A0 .probe =A0 =A0 =A0 =A0 =A0=3D of_mpc83xx_spi_probe,
> - =A0 =A0 =A0 .remove =A0 =A0 =A0 =A0 =3D __devexit_p(of_mpc83xx_spi_remo=
ve),
> +static struct of_platform_driver of_mpc8xxx_spi_driver =3D {
> + =A0 =A0 =A0 .name =A0 =A0 =A0 =A0 =A0 =3D "mpc8xxx_spi",
> + =A0 =A0 =A0 .match_table =A0 =A0=3D of_mpc8xxx_spi_match,
> + =A0 =A0 =A0 .probe =A0 =A0 =A0 =A0 =A0=3D of_mpc8xxx_spi_probe,
> + =A0 =A0 =A0 .remove =A0 =A0 =A0 =A0 =3D __devexit_p(of_mpc8xxx_spi_remo=
ve),
> =A0};
>
> =A0#ifdef CONFIG_MPC832x_RDB
> @@ -882,7 +882,7 @@ static struct of_platform_driver of_mpc83xx_spi_drive=
r =3D {
> =A0* tree can work with OpenFirmware driver. But for now we support old t=
rees
> =A0* as well.
> =A0*/
> -static int __devinit plat_mpc83xx_spi_probe(struct platform_device *pdev=
)
> +static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev=
)
> =A0{
> =A0 =A0 =A0 =A0struct resource *mem;
> =A0 =A0 =A0 =A0unsigned int irq;
> @@ -899,21 +899,21 @@ static int __devinit plat_mpc83xx_spi_probe(struct =
platform_device *pdev)
> =A0 =A0 =A0 =A0if (!irq)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return -EINVAL;
>
> - =A0 =A0 =A0 master =3D mpc83xx_spi_probe(&pdev->dev, mem, irq);
> + =A0 =A0 =A0 master =3D mpc8xxx_spi_probe(&pdev->dev, mem, irq);
> =A0 =A0 =A0 =A0if (IS_ERR(master))
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return PTR_ERR(master);
> =A0 =A0 =A0 =A0return 0;
> =A0}
>
> -static int __devexit plat_mpc83xx_spi_remove(struct platform_device *pde=
v)
> +static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pde=
v)
> =A0{
> - =A0 =A0 =A0 return mpc83xx_spi_remove(&pdev->dev);
> + =A0 =A0 =A0 return mpc8xxx_spi_remove(&pdev->dev);
> =A0}
>
> =A0MODULE_ALIAS("platform:mpc83xx_spi");
> -static struct platform_driver mpc83xx_spi_driver =3D {
> - =A0 =A0 =A0 .probe =3D plat_mpc83xx_spi_probe,
> - =A0 =A0 =A0 .remove =3D __exit_p(plat_mpc83xx_spi_remove),
> +static struct platform_driver mpc8xxx_spi_driver =3D {
> + =A0 =A0 =A0 .probe =3D plat_mpc8xxx_spi_probe,
> + =A0 =A0 =A0 .remove =3D __exit_p(plat_mpc8xxx_spi_remove),
> =A0 =A0 =A0 =A0.driver =3D {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0.name =3D "mpc83xx_spi",
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0.owner =3D THIS_MODULE,
> @@ -924,35 +924,35 @@ static bool legacy_driver_failed;
>
> =A0static void __init legacy_driver_register(void)
> =A0{
> - =A0 =A0 =A0 legacy_driver_failed =3D platform_driver_register(&mpc83xx_=
spi_driver);
> + =A0 =A0 =A0 legacy_driver_failed =3D platform_driver_register(&mpc8xxx_=
spi_driver);
> =A0}
>
> =A0static void __exit legacy_driver_unregister(void)
> =A0{
> =A0 =A0 =A0 =A0if (legacy_driver_failed)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return;
> - =A0 =A0 =A0 platform_driver_unregister(&mpc83xx_spi_driver);
> + =A0 =A0 =A0 platform_driver_unregister(&mpc8xxx_spi_driver);
> =A0}
> =A0#else
> =A0static void __init legacy_driver_register(void) {}
> =A0static void __exit legacy_driver_unregister(void) {}
> =A0#endif /* CONFIG_MPC832x_RDB */
>
> -static int __init mpc83xx_spi_init(void)
> +static int __init mpc8xxx_spi_init(void)
> =A0{
> =A0 =A0 =A0 =A0legacy_driver_register();
> - =A0 =A0 =A0 return of_register_platform_driver(&of_mpc83xx_spi_driver);
> + =A0 =A0 =A0 return of_register_platform_driver(&of_mpc8xxx_spi_driver);
> =A0}
>
> -static void __exit mpc83xx_spi_exit(void)
> +static void __exit mpc8xxx_spi_exit(void)
> =A0{
> - =A0 =A0 =A0 of_unregister_platform_driver(&of_mpc83xx_spi_driver);
> + =A0 =A0 =A0 of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
> =A0 =A0 =A0 =A0legacy_driver_unregister();
> =A0}
>
> -module_init(mpc83xx_spi_init);
> -module_exit(mpc83xx_spi_exit);
> +module_init(mpc8xxx_spi_init);
> +module_exit(mpc8xxx_spi_exit);
>
> =A0MODULE_AUTHOR("Kumar Gala");
> -MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
> +MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
> =A0MODULE_LICENSE("GPL");
> --
> 1.6.2.2
>
> -------------------------------------------------------------------------=
-----
> Register Now & Save for Velocity, the Web Performance & Operations
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> expert-led, hands-on workshops and two days of sessions from industry
> leaders in dedicated Performance & Operations tracks. Use code vel09scf
> and Save an extra 15% before 5/3. http://p.sf.net/sfu/velocityconf
> _______________________________________________
> spi-devel-general mailing list
> spi-devel-general@lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/spi-devel-general
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH 2/2] Added AMCC 460EX Canyonlands SATA support.
From: Grant Likely @ 2009-05-01 21:35 UTC (permalink / raw)
To: Feng Kan; +Cc: linuxppc-dev, linux-ide
In-Reply-To: <1241211774-32719-1-git-send-email-fkan@amcc.com>
On Fri, May 1, 2009 at 3:02 PM, Feng Kan <fkan@amcc.com> wrote:
> This adds the OF platform support for the AMCC 460EX Canyonlands SATA por=
t.
>
> Signed-off-by: Feng Kan <fkan@amcc.com>
> ---
> =A0arch/powerpc/boot/dts/canyonlands.dts =A0| =A0 =A08 ++
> =A0arch/powerpc/platforms/44x/Makefile =A0 =A0| =A0 =A04 +
> =A0arch/powerpc/platforms/44x/amcc-sata.c | =A0125 ++++++++++++++++++++++=
++++++++++
> =A03 files changed, 137 insertions(+), 0 deletions(-)
> =A0create mode 100644 arch/powerpc/platforms/44x/amcc-sata.c
>
> diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dt=
s/canyonlands.dts
> index 5fd1ad0..b536223 100644
> --- a/arch/powerpc/boot/dts/canyonlands.dts
> +++ b/arch/powerpc/boot/dts/canyonlands.dts
> @@ -163,6 +163,14 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 interrupts =3D <0x1e 4>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
>
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0SATA0: sata@bffd1000 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "amcc,sat=
a-460ex";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <4 0xbffd1000 0x800=
4 0xbffd0800 0x400>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D <&U=
IC3>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <0 4 =A0 =
=A0 =A0 /* SATA */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A05 4>; =A0 =A0 /* AHBDMA */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
> +
You should also add documentation for the "amcc,sata-460ex" binding to
Documentation/powerpc/dts-bindings. Doesn't have to be huge, just a
blurb describing the device and what each tuple in the reg &
interrupts properties mean.
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH v6] introduce macro spin_event_timeout()
From: Sean MacLennan @ 2009-05-01 21:33 UTC (permalink / raw)
To: Timur Tabi; +Cc: scottwood, linuxppc-dev
In-Reply-To: <1240859144-20893-1-git-send-email-timur@freescale.com>
On Mon, 27 Apr 2009 14:05:44 -0500
"Timur Tabi" <timur@freescale.com> wrote:
> +#define spin_event_timeout(condition, timeout, delay,
> rc) \
> +{ \
> + unsigned long __loops = tb_ticks_per_usec *
> timeout; \
> + unsigned long __start =
> get_tbl(); \
> + while (!(rc = (condition)) && (tb_ticks_since(__start) <=
> __loops)) \
> + udelay(delay);
> \ +}
> +
Would cpu_relax be a good thing to put here?
Something like:
while (!(rc = (condition)) && (tb_ticks_since(__start) <= __loops)) \
if (delay) \
udelay(delay); \
else \
cpu_relax(); \
Cheers,
Sean
^ permalink raw reply
* Re: [PATCH 1/2] Added support for Designware SATA controller driver
From: Scott Wood @ 2009-05-01 21:26 UTC (permalink / raw)
To: Feng Kan; +Cc: Mark Miesfeld, linuxppc-dev, linux-ide
In-Reply-To: <1241211767-32697-1-git-send-email-fkan@amcc.com>
Feng Kan wrote:
> This adds support for the Designware SATA controller.
>
> Signed-off-by: Feng Kan <fkan@amcc.com>
> Signed-off-by: Mark Miesfeld <miesfeld@gmail.com>
> ---
> drivers/ata/Kconfig | 10 +
> drivers/ata/Makefile | 1 +
> drivers/ata/sata_dwc.c | 2053 ++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 2064 insertions(+), 0 deletions(-)
> create mode 100644 drivers/ata/sata_dwc.c
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 0bcf264..c3d0b24 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -72,6 +72,16 @@ config SATA_FSL
>
> If unsure, say N.
>
> +config SATA_DWC
> + tristate "DesignWare Cores SATA support"
> + depends on 460EX
That "depends" looks too specific -- we don't want to grow a list if
this controller gets added to other chips.
Only depend on what this driver actually needs in order to function.
-Scott
^ permalink raw reply
* [PATCH 0/2] Added support for Designware SATA controller driver
From: Feng Kan @ 2009-05-01 21:06 UTC (permalink / raw)
To: linuxppc-dev, linux-ide; +Cc: sr, Feng Kan
Fixed comment issue. Change goto statements to lower case. Also
fixed the Kconfig problem.
I don't know if I need to add Stefan Roese for the signoff, since he
did the of platform part.
Stefan, if you see this please let me know.
Feng Kan
^ permalink raw reply
* [PATCH 2/2] Added AMCC 460EX Canyonlands SATA support.
From: Feng Kan @ 2009-05-01 21:02 UTC (permalink / raw)
To: linuxppc-dev, linux-ide; +Cc: Feng Kan
This adds the OF platform support for the AMCC 460EX Canyonlands SATA port.
Signed-off-by: Feng Kan <fkan@amcc.com>
---
arch/powerpc/boot/dts/canyonlands.dts | 8 ++
arch/powerpc/platforms/44x/Makefile | 4 +
arch/powerpc/platforms/44x/amcc-sata.c | 125 ++++++++++++++++++++++++++++++++
3 files changed, 137 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/44x/amcc-sata.c
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 5fd1ad0..b536223 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -163,6 +163,14 @@
interrupts = <0x1e 4>;
};
+ SATA0: sata@bffd1000 {
+ compatible = "amcc,sata-460ex";
+ reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
+ interrupt-parent = <&UIC3>;
+ interrupts = <0 4 /* SATA */
+ 5 4>; /* AHBDMA */
+ };
+
POB0: opb {
compatible = "ibm,opb-460ex", "ibm,opb";
#address-cells = <1>;
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 01f51da..fa0a999 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -4,3 +4,7 @@ obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_SAM440EP) += sam440ep.o
obj-$(CONFIG_WARP) += warp.o
obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
+ifeq ($(CONFIG_SATA_DWC),y)
+obj-$(CONFIG_CANYONLANDS) += amcc-sata.o
+endif
+
diff --git a/arch/powerpc/platforms/44x/amcc-sata.c b/arch/powerpc/platforms/44x/amcc-sata.c
new file mode 100644
index 0000000..fdda917
--- /dev/null
+++ b/arch/powerpc/platforms/44x/amcc-sata.c
@@ -0,0 +1,125 @@
+/*
+ * AMCC Canyonlands SATA wrapper
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * Extract the resources (MEM & IRQ) from the dts file and put them
+ * into the platform-device struct for usage in the platform-device
+ * SATA driver.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+
+/*
+ * Resource template will be filled dynamically with the values
+ * extracted from the dts file
+ */
+static struct resource sata_resources[] = {
+ [0] = {
+ /* 460EX SATA registers */
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ /* 460EX AHBDMA registers */
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ /* 460EX SATA IRQ */
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ /* 460EX AHBDMA IRQ */
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 dma_mask = 0xffffffffULL;
+
+static struct platform_device sata_device = {
+ .name = "sata-dwc",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(sata_resources),
+ .resource = sata_resources,
+ .dev = {
+ .dma_mask = &dma_mask,
+ .coherent_dma_mask = 0xffffffffULL,
+ }
+};
+
+static struct platform_device *ppc460ex_devs[] __initdata = {
+ &sata_device,
+};
+
+static int __devinit ppc460ex_sata_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ struct device_node *np = ofdev->node;
+ struct resource res;
+ const char *val;
+
+ /*
+ * Check if device is enabled
+ */
+ val = of_get_property(np, "status", NULL);
+ if (val && !strcmp(val, "disabled")) {
+ printk(KERN_INFO "SATA port disabled via device-tree\n");
+ return 0;
+ }
+
+ /*
+ * Extract register address reange from device tree and put it into
+ * the platform device structure
+ */
+ if (of_address_to_resource(np, 0, &res)) {
+ printk(KERN_ERR "%s: Can't get SATA register address\n",
+ __func__);
+ return -ENOMEM;
+ }
+ sata_resources[0].start = res.start;
+ sata_resources[0].end = res.end;
+
+ if (of_address_to_resource(np, 1, &res)) {
+ printk(KERN_ERR "%s: Can't get AHBDMA register address\n",
+ __func__);
+ return -ENOMEM;
+ }
+ sata_resources[1].start = res.start;
+ sata_resources[1].end = res.end;
+
+ /*
+ * Extract IRQ number(s) from device tree and put them into
+ * the platform device structure
+ */
+ sata_resources[2].start = sata_resources[2].end =
+ irq_of_parse_and_map(np, 0);
+ sata_resources[3].start = sata_resources[3].end =
+ irq_of_parse_and_map(np, 1);
+
+ return platform_add_devices(ppc460ex_devs, ARRAY_SIZE(ppc460ex_devs));
+}
+
+static int __devexit ppc460ex_sata_remove(struct of_device *ofdev)
+{
+ /* Nothing to do here */
+ return 0;
+}
+
+static const struct of_device_id ppc460ex_sata_match[] = {
+ { .compatible = "amcc,sata-460ex", },
+ {}
+};
+
+static struct of_platform_driver ppc460ex_sata_driver = {
+ .name = "sata-460ex",
+ .match_table = ppc460ex_sata_match,
+ .probe = ppc460ex_sata_probe,
+ .remove = ppc460ex_sata_remove,
+};
+
+static int __init ppc460ex_sata_init(void)
+{
+ return of_register_platform_driver(&ppc460ex_sata_driver);
+}
+device_initcall(ppc460ex_sata_init);
--
1.5.5
^ permalink raw reply related
* [PATCH 1/2] Added support for Designware SATA controller driver
From: Feng Kan @ 2009-05-01 21:02 UTC (permalink / raw)
To: linuxppc-dev, linux-ide; +Cc: Mark Miesfeld, Feng Kan
This adds support for the Designware SATA controller.
Signed-off-by: Feng Kan <fkan@amcc.com>
Signed-off-by: Mark Miesfeld <miesfeld@gmail.com>
---
drivers/ata/Kconfig | 10 +
drivers/ata/Makefile | 1 +
drivers/ata/sata_dwc.c | 2053 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 2064 insertions(+), 0 deletions(-)
create mode 100644 drivers/ata/sata_dwc.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 0bcf264..c3d0b24 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -72,6 +72,16 @@ config SATA_FSL
If unsure, say N.
+config SATA_DWC
+ tristate "DesignWare Cores SATA support"
+ depends on 460EX
+ help
+ This option enables support for the Synopsys DesignWare Cores SATA
+ controller.
+ It can be found on the AMCC 460EX.
+
+ If unsure, say N.
+
config ATA_SFF
bool "ATA SFF support"
default y
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 7f1ecf9..3d41fc7 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
obj-$(CONFIG_SATA_FSL) += sata_fsl.o
+obj-$(CONFIG_SATA_DWC) += sata_dwc.o
obj-$(CONFIG_PATA_ALI) += pata_ali.o
obj-$(CONFIG_PATA_AMD) += pata_amd.o
diff --git a/drivers/ata/sata_dwc.c b/drivers/ata/sata_dwc.c
new file mode 100644
index 0000000..f6f97da
--- /dev/null
+++ b/drivers/ata/sata_dwc.c
@@ -0,0 +1,2053 @@
+/*
+ * drivers/ata/sata_dwc.c
+ *
+ * Synopsys DesignWare Cores (DWC) SATA host driver
+ *
+ * Author: Mark Miesfeld <mmiesfeld@amcc.com>
+ *
+ * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
+ * Copyright 2008 DENX Software Engineering
+ *
+ * Based on versions provided by AMCC and Synopsys which are:
+ * Copyright 2006 Applied Micro Circuits Corporation
+ * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#ifdef CONFIG_SATA_DWC_DEBUG
+#define DEBUG
+#endif
+
+#ifdef CONFIG_SATA_DWC_VDEBUG
+#define VERBOSE_DEBUG
+#define DEBUG_NCQ
+#endif
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/libata.h>
+
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_cmnd.h>
+
+#define DRV_NAME "sata-dwc"
+#define DRV_VERSION "1.0"
+
+/* SATA DMA driver Globals */
+#define DMA_NUM_CHANS 1
+#define DMA_NUM_CHAN_REGS 8
+
+/* SATA DMA Register definitions */
+#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
+
+struct dmareg {
+ u32 low; /* Low bits 0-31 */
+ u32 high; /* High bits 32-63 */
+};
+
+/* DMA Per Channel registers */
+
+struct dma_chan_regs {
+ struct dmareg sar; /* Source Address */
+ struct dmareg dar; /* Destination address */
+ struct dmareg llp; /* Linked List Pointer */
+ struct dmareg ctl; /* Control */
+ struct dmareg sstat; /* Source Status not implemented in core */
+ struct dmareg dstat; /* Destination Status not implemented in core */
+ struct dmareg sstatar; /* Source Status Address not impl in core */
+ struct dmareg dstatar; /* Destination Status Address not implemented */
+ struct dmareg cfg; /* Config */
+ struct dmareg sgr; /* Source Gather */
+ struct dmareg dsr; /* Destination Scatter */
+};
+
+/* Generic Interrupt Registers */
+struct dma_interrupt_regs {
+ struct dmareg tfr; /* Transfer Interrupt */
+ struct dmareg block; /* Block Interrupt */
+ struct dmareg srctran; /* Source Transfer Interrupt */
+ struct dmareg dsttran; /* Dest Transfer Interrupt */
+ struct dmareg error; /* Error */
+};
+
+struct ahb_dma_regs {
+ struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
+ struct dma_interrupt_regs interrupt_raw; /* Raw Interrupt */
+ struct dma_interrupt_regs interrupt_status; /* Interrupt Status */
+ struct dma_interrupt_regs interrupt_mask; /* Interrupt Mask */
+ struct dma_interrupt_regs interrupt_clear; /* Interrupt Clear */
+ struct dmareg statusInt; /* Interrupt combined */
+ struct dmareg rq_srcreg; /* Src Trans Req */
+ struct dmareg rq_dstreg; /* Dst Trans Req */
+ struct dmareg rq_sgl_srcreg; /* Sngl Src Trans Req */
+ struct dmareg rq_sgl_dstreg; /* Sngl Dst Trans Req */
+ struct dmareg rq_lst_srcreg; /* Last Src Trans Req */
+ struct dmareg rq_lst_dstreg; /* Last Dst Trans Req */
+ struct dmareg dma_cfg; /* DMA Config */
+ struct dmareg dma_chan_en; /* DMA Channel Enable */
+ struct dmareg dma_id; /* DMA ID */
+ struct dmareg dma_test; /* DMA Test */
+ struct dmareg res1; /* reserved */
+ struct dmareg res2; /* reserved */
+
+ /* DMA Comp Params
+ * Param 6 = dma_param[0], Param 5 = dma_param[1],
+ * Param 4 = dma_param[2] ...
+ */
+ struct dmareg dma_params[6];
+};
+
+/* Data structure for linked list item */
+struct lli {
+ u32 sar; /* Source Address */
+ u32 dar; /* Destination address */
+ u32 llp; /* Linked List Pointer */
+ struct dmareg ctl; /* Control */
+ struct dmareg dstat; /* Destination Status */
+};
+
+#define SATA_DWC_DMAC_LLI_SZ (sizeof(struct lli))
+#define SATA_DWC_DMAC_LLI_NUM 256
+#define SATA_DWC_DMAC_TWIDTH_BYTES 4
+#define SATA_DWC_DMAC_LLI_TBL_SZ \
+ (SATA_DWC_DMAC_LLI_SZ * SATA_DWC_DMAC_LLI_NUM)
+#define SATA_DWC_DMAC_CTRL_TSIZE_MAX \
+ (0x00000800 * SATA_DWC_DMAC_TWIDTH_BYTES)
+
+/* DMA Register Operation Bits */
+#define DMA_EN 0x00000001 /* Enable AHB DMA */
+#define DMA_CHANNEL(ch) (0x00000001 << (ch)) /* Select channel */
+#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
+ ((0x000000001 << (ch)) << 8))
+#define DMA_DISABLE_CHAN(ch) (0x00000000 | ((0x000000001 << (ch)) << 8))
+
+/* Channel Control Register */
+#define DMA_CTL_BLK_TS(size) ((size) & 0x000000FFF) /* Blk Transfer size */
+#define DMA_CTL_LLP_SRCEN 0x10000000 /* Blk chain enable Src */
+#define DMA_CTL_LLP_DSTEN 0x08000000 /* Blk chain enable Dst */
+/*
+ * This define is used to set block chaining disabled in the control low
+ * register. It is already in little endian format so it can be &'d dirctly.
+ * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
+ */
+#define DMA_CTL_LLP_DISABLE_LE32 0xffffffe7
+#define DMA_CTL_SMS(num) ((num & 0x3) << 25) /*Src Master Select*/
+#define DMA_CTL_DMS(num) ((num & 0x3) << 23) /*Dst Master Select*/
+#define DMA_CTL_TTFC(type) ((type & 0x7) << 20) /*Type&Flow cntr*/
+#define DMA_CTL_TTFC_P2M_DMAC 0x00000002 /*Per mem,DMAC cntr*/
+#define DMA_CTL_TTFC_M2P_PER 0x00000003 /*Mem per,peri cntr*/
+#define DMA_CTL_SRC_MSIZE(size) ((size & 0x7) << 14) /*Src Burst Len*/
+#define DMA_CTL_DST_MSIZE(size) ((size & 0x7) << 11) /*Dst Burst Len*/
+#define DMA_CTL_SINC_INC 0x00000000 /*Src addr incr*/
+#define DMA_CTL_SINC_DEC 0x00000200
+#define DMA_CTL_SINC_NOCHANGE 0x00000400
+#define DMA_CTL_DINC_INC 0x00000000 /*Dst addr incr*/
+#define DMA_CTL_DINC_DEC 0x00000080
+#define DMA_CTL_DINC_NOCHANGE 0x00000100
+#define DMA_CTL_SRC_TRWID(size) ((size & 0x7) << 4) /*Src Trnsfr Width*/
+#define DMA_CTL_DST_TRWID(size) ((size & 0x7) << 1) /*Dst Trnsfr Width*/
+#define DMA_CTL_INT_EN 0x00000001 /*Interrupt Enable*/
+
+/* Channel Configuration Register high bits */
+#define DMA_CFG_FCMOD_REQ 0x00000001 /*Flow cntrl req*/
+#define DMA_CFG_PROTCTL (0x00000003 << 2) /*Protection cntrl*/
+
+/* Channel Configuration Register low bits */
+#define DMA_CFG_RELD_DST 0x80000000 /*Reload Dst/Src Addr*/
+#define DMA_CFG_RELD_SRC 0x40000000
+#define DMA_CFG_HS_SELSRC 0x00000800 /*SW hndshk Src/Dst*/
+#define DMA_CFG_HS_SELDST 0x00000400
+#define DMA_CFG_FIFOEMPTY (0x00000001 << 9) /*FIFO Empty bit*/
+
+/* Assign hardware handshaking interface (x) to dst / sre peripheral */
+#define DMA_CFG_HW_HS_DEST(int_num) ((int_num & 0xF) << 11)
+#define DMA_CFG_HW_HS_SRC(int_num) ((int_num & 0xF) << 7)
+
+/* Channel Linked List Pointer Register */
+#define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
+#define DMA_LLP_AHBMASTER1 0 /* List Master Select */
+#define DMA_LLP_AHBMASTER2 1
+
+#define SATA_DWC_MAX_PORTS 1
+
+#define SATA_DWC_SCR_OFFSET 0x24
+#define SATA_DWC_REG_OFFSET 0x64
+
+/* DWC SATA Registers */
+struct sata_dwc_regs {
+ u32 fptagr; /* 1st party DMA tag */
+ u32 fpbor; /* 1st party DMA buffer offset */
+ u32 fptcr; /* 1st party DMA Xfr count */
+ u32 dmacr; /* DMA Control */
+ u32 dbtsr; /* DMA Burst Transac size */
+ u32 intpr; /* Interrupt Pending */
+ u32 intmr; /* Interrupt Mask */
+ u32 errmr; /* Error Mask */
+ u32 llcr; /* Link Layer Control */
+ u32 phycr; /* PHY Control */
+ u32 physr; /* PHY Status */
+ u32 rxbistpd; /* Recvd BIST pattern def register */
+ u32 rxbistpd1; /* Recvd BIST data dword1 */
+ u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
+ u32 txbistpd; /* Trans BIST pattern def register */
+ u32 txbistpd1; /* Trans BIST data dword1 */
+ u32 txbistpd2; /* Trans BIST data dword2 */
+ u32 bistcr; /* BIST Control Register */
+ u32 bistfctr; /* BIST FIS Count Register */
+ u32 bistsr; /* BIST Status Register */
+ u32 bistdecr; /* BIST Dword Error count register */
+ u32 res[15]; /* Reserved locations */
+ u32 testr; /* Test Register */
+ u32 versionr; /* Version Register */
+ u32 idr; /* ID Register */
+ u32 unimpl[192]; /* Unimplemented */
+ u32 dmadr[256]; /* FIFO Locations in DMA Mode */
+};
+
+#define SCR_SCONTROL_DET_ENABLE 0x00000001
+#define SCR_SSTATUS_DET_PRESENT 0x00000001
+#define SCR_SERROR_DIAG_X 0x04000000
+
+/* DWC SATA Register Operations */
+#define SATA_DWC_TXFIFO_DEPTH 0x01FF
+#define SATA_DWC_RXFIFO_DEPTH 0x01FF
+
+#define SATA_DWC_DMACR_TMOD_TXCHEN 0x00000004
+#define SATA_DWC_DMACR_TXCHEN (0x00000001 | \
+ SATA_DWC_DMACR_TMOD_TXCHEN)
+#define SATA_DWC_DMACR_RXCHEN (0x00000002 | \
+ SATA_DWC_DMACR_TMOD_TXCHEN)
+#define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) | \
+ SATA_DWC_DMACR_TMOD_TXCHEN)
+#define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) | \
+ SATA_DWC_DMACR_TMOD_TXCHEN)
+#define SATA_DWC_DMACR_TXRXCH_CLEAR SATA_DWC_DMACR_TMOD_TXCHEN
+
+#define SATA_DWC_DBTSR_MWR(size) ((size/4) & \
+ SATA_DWC_TXFIFO_DEPTH)
+#define SATA_DWC_DBTSR_MRD(size) (((size/4) & \
+ SATA_DWC_RXFIFO_DEPTH) << 16)
+#define SATA_DWC_INTPR_DMAT 0x00000001
+#define SATA_DWC_INTPR_NEWFP 0x00000002
+#define SATA_DWC_INTPR_PMABRT 0x00000004
+#define SATA_DWC_INTPR_ERR 0x00000008
+#define SATA_DWC_INTPR_NEWBIST 0x00000010
+#define SATA_DWC_INTPR_IPF 0x10000000
+#define SATA_DWC_INTMR_DMATM 0x00000001
+#define SATA_DWC_INTMR_NEWFPM 0x00000002
+#define SATA_DWC_INTMR_PMABRTM 0x00000004
+#define SATA_DWC_INTMR_ERRM 0x00000008
+#define SATA_DWC_INTMR_NEWBISTM 0x00000010
+#define SATA_DWC_LLCR_SCRAMEN 0x00000001
+#define SATA_DWC_LLCR_DESCRAMEN 0x00000002
+#define SATA_DWC_LLCR_RPDEN 0x00000004
+
+/* This is all error bits, zero's are reserved fields. */
+#define SATA_DWC_SERROR_ERR_BITS 0x0FFF0F03
+
+#define SATA_DWC_SCR0_SPD_GET(v) ((v >> 4) & 0x0000000F)
+
+struct sata_dwc_device {
+ struct device *dev; /* generic device struct */
+ struct ata_probe_ent *pe; /* ptr to probe-ent */
+ struct ata_host *host;
+ u8 *reg_base;
+ struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
+ int irq_dma;
+};
+
+#define SATA_DWC_QCMD_MAX 32
+
+struct sata_dwc_device_port {
+ struct sata_dwc_device *hsdev;
+ int cmd_issued[SATA_DWC_QCMD_MAX];
+ struct lli *llit[SATA_DWC_QCMD_MAX];
+ dma_addr_t llit_dma[SATA_DWC_QCMD_MAX];
+ u32 dma_chan[SATA_DWC_QCMD_MAX];
+ int dma_pending[SATA_DWC_QCMD_MAX];
+};
+
+/*
+ * Commonly used DWC SATA driver Macros
+ */
+#define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *) \
+ (host)->private_data)
+#define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *) \
+ (ap)->host->private_data)
+#define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *) \
+ (ap)->private_data)
+#define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *) \
+ (qc)->ap->host->private_data)
+#define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *) \
+ (hsdevp)->hsdev)
+
+enum {
+ SATA_DWC_CMD_ISSUED_NOT = 0,
+ SATA_DWC_CMD_ISSUED_PEND = 1,
+ SATA_DWC_CMD_ISSUED_EXEC = 2,
+ SATA_DWC_CMD_ISSUED_NODATA = 3,
+
+ SATA_DWC_DMA_PEND_NONE = 0,
+ SATA_DWC_DMA_PEND_TX = 1,
+ SATA_DWC_DMA_PEND_RX = 2,
+};
+
+/*
+ * Globals
+ */
+static u32 sata_dwc_sactive_issued; /* issued queued ops */
+static u32 sata_dwc_sactive_queued; /* queued ops */
+static struct ahb_dma_regs *sata_dma_regs;
+static u32 dma_interrupt_count;
+static void *scr_addr_sstatus;
+static struct device *dwc_dev;
+
+/*
+ * Prototypes
+ */
+static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
+static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
+ u32 check_status);
+static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
+static void sata_dwc_port_stop(struct ata_port *ap);
+static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
+
+static int dma_dwc_init(struct sata_dwc_device *hsdev, struct resource *res,
+ int irq);
+static void dma_dwc_exit(struct sata_dwc_device *hsdev);
+static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
+ struct lli *lli, dma_addr_t dma_lli,
+ void __iomem *addr, int dir);
+static void dma_dwc_xfer_start(int dma_ch);
+static void dma_dwc_terminate_dma(int dma_ch);
+
+static const char *dir_2_txt(enum dma_data_direction dir)
+{
+ switch (dir) {
+ case DMA_BIDIRECTIONAL:
+ return "bi";
+ case DMA_FROM_DEVICE:
+ return "from";
+ case DMA_TO_DEVICE:
+ return "to";
+ case DMA_NONE:
+ return "none";
+ default:
+ return "err";
+ }
+}
+
+static const char *prot_2_txt(enum ata_tf_protocols protocol)
+{
+ switch (protocol) {
+ case ATA_PROT_UNKNOWN:
+ return "unknown";
+ case ATA_PROT_NODATA:
+ return "nodata";
+ case ATA_PROT_PIO:
+ return "pio";
+ case ATA_PROT_DMA:
+ return "dma";
+ case ATA_PROT_NCQ:
+ return "ncq";
+ case ATAPI_PROT_PIO:
+ return "atapi pio";
+ case ATAPI_PROT_NODATA:
+ return "atapi nodata";
+ case ATAPI_PROT_DMA:
+ return "atapi dma";
+ default:
+ return "err";
+ }
+}
+
+inline const char *ata_cmd_2_txt(const struct ata_taskfile *tf)
+{
+ switch (tf->command) {
+ case ATA_CMD_CHK_POWER:
+ return "ATA_CMD_CHK_POWER";
+ case ATA_CMD_EDD:
+ return "ATA_CMD_EDD";
+ case ATA_CMD_FLUSH:
+ return "ATA_CMD_FLUSH";
+ case ATA_CMD_FLUSH_EXT:
+ return "ATA_CMD_FLUSH_EXT";
+ case ATA_CMD_ID_ATA:
+ return "ATA_CMD_ID_ATA";
+ case ATA_CMD_ID_ATAPI:
+ return "ATA_CMD_ID_ATAPI";
+ case ATA_CMD_FPDMA_READ:
+ return "ATA_CMD_FPDMA_READ";
+ case ATA_CMD_FPDMA_WRITE:
+ return "ATA_CMD_FPDMA_WRITE";
+ case ATA_CMD_READ:
+ return "ATA_CMD_READ";
+ case ATA_CMD_READ_EXT:
+ return "ATA_CMD_READ_EXT";
+ case ATA_CMD_WRITE:
+ return "ATA_CMD_WRITE";
+ case ATA_CMD_WRITE_EXT:
+ return "ATA_CMD_WRITE_EXT";
+ case ATA_CMD_PIO_READ:
+ return "ATA_CMD_PIO_READ";
+ case ATA_CMD_PIO_READ_EXT:
+ return "ATA_CMD_PIO_READ_EXT";
+ case ATA_CMD_PIO_WRITE:
+ return "ATA_CMD_PIO_WRITE";
+ case ATA_CMD_PIO_WRITE_EXT:
+ return "ATA_CMD_PIO_WRITE_EXT";
+ case ATA_CMD_SET_FEATURES:
+ return "ATA_CMD_SET_FEATURES";
+ case ATA_CMD_PACKET:
+ return "ATA_CMD_PACKET";
+ default:
+ return "ATA_CMD_???";
+ }
+}
+
+static void sata_dwc_tf_dump(struct ata_taskfile *tf)
+{
+ dev_vdbg(dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx"
+ "device: %x\n", tf->command, prot_2_txt(tf->protocol),
+ tf->flags, tf->device);
+ dev_vdbg(dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam:"
+ "0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
+ tf->lbam, tf->lbah);
+ dev_vdbg(dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x "
+ "hob_lbam: 0x%x hob_lbah: 0x%x\n", tf->hob_feature,
+ tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
+ tf->hob_lbah);
+}
+
+/*
+ * Function: get_burst_length_encode
+ * arguments: datalength: length in bytes of data
+ * returns value to be programmed in register corrresponding to data length
+ * This value is effectively the log(base 2) of the length
+ */
+static inline int get_burst_length_encode(int datalength)
+{
+ int items = datalength >> 2; /* div by 4 to get lword count */
+
+ if (items >= 64)
+ return 5;
+
+ if (items >= 32)
+ return 4;
+
+ if (items >= 16)
+ return 3;
+
+ if (items >= 8)
+ return 2;
+
+ if (items >= 4)
+ return 1;
+
+ return 0;
+}
+
+static inline void clear_chan_interrupts(int c)
+{
+ out_le32(&(sata_dma_regs->interrupt_clear.tfr.low), DMA_CHANNEL(c));
+ out_le32(&(sata_dma_regs->interrupt_clear.block.low), DMA_CHANNEL(c));
+ out_le32(&(sata_dma_regs->interrupt_clear.srctran.low), DMA_CHANNEL(c));
+ out_le32(&(sata_dma_regs->interrupt_clear.dsttran.low), DMA_CHANNEL(c));
+ out_le32(&(sata_dma_regs->interrupt_clear.error.low), DMA_CHANNEL(c));
+}
+
+/*
+ * Function: dma_request_channel
+ * arguments: None
+ * returns channel number if available else -1
+ * This function assigns the next available DMA channel from the list to the
+ * requester
+ */
+static int dma_request_channel(void)
+{
+ int i;
+ struct ahb_dma_regs *pdma;
+
+ pdma = sata_dma_regs;
+ for (i = 0; i < DMA_NUM_CHANS; i++) {
+ if (!(in_le32(&(pdma->dma_chan_en.low)) & DMA_CHANNEL(i)))
+ return i;
+ }
+
+ dev_err(dwc_dev, "%s NO channel chan_en: 0x%08x\n", __func__,
+ in_le32(&(pdma->dma_chan_en.low)));
+
+ return -1;
+}
+
+/*
+ * Function: dma_dwc_interrupt
+ * arguments: irq, dev_id, pt_regs
+ * returns channel number if available else -1
+ * Interrupt Handler for DW AHB SATA DMA
+ */
+static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
+{
+ int chan;
+ u32 tfr_reg, err_reg;
+ unsigned long flags;
+ struct sata_dwc_device *hsdev =
+ (struct sata_dwc_device *)hsdev_instance;
+ struct ata_host *host = (struct ata_host *)hsdev->host;
+ struct ata_port *ap;
+ struct sata_dwc_device_port *hsdevp;
+ u8 tag = 0;
+ unsigned int port = 0;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ ap = host->ports[port];
+ hsdevp = HSDEVP_FROM_AP(ap);
+ tag = ap->link.active_tag;
+
+ tfr_reg = in_le32(&(sata_dma_regs->interrupt_status.tfr.low));
+ err_reg = in_le32(&(sata_dma_regs->interrupt_status.error.low));
+
+ dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
+ tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
+
+ for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
+ /* Check for end-of-transfer interrupt. */
+ if (tfr_reg & DMA_CHANNEL(chan)) {
+ /*
+ *Each DMA command produces 2 interrupts. Only
+ * complete the command after both interrupts have been
+ * seen. (See sata_dwc_isr())
+ */
+ dma_interrupt_count++;
+
+ sata_dwc_clear_dmacr(hsdevp, tag);
+
+ if (hsdevp->dma_pending[tag] == 0) {
+ dev_err(ap->dev, "DMA not pending eot=0x%08x "
+ "err=0x%08x tag=0x%02x pending=%d\n",
+ tfr_reg, err_reg, tag,
+ hsdevp->dma_pending[tag]);
+ }
+
+ if ((dma_interrupt_count % 2) == 0)
+ sata_dwc_dma_xfer_complete(ap, 1);
+
+ /* Clear the interrupt */
+ out_le32(&(sata_dma_regs->interrupt_clear.tfr.low),
+ DMA_CHANNEL(chan));
+ }
+
+ /* Check for error interrupt. */
+ if (err_reg & DMA_CHANNEL(chan)) {
+ /* TODO Need error handler ! */
+ dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
+ err_reg);
+
+ /* Clear the interrupt. */
+ out_le32(&(sata_dma_regs->interrupt_clear.error.low),
+ DMA_CHANNEL(chan));
+ }
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+ return IRQ_HANDLED;
+}
+
+/*
+ * Function: dma_request_interrupts
+ * arguments: hsdev
+ * returns status
+ * This function registers ISR for a particular DMA channel interrupt
+ */
+static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
+{
+ int retval = 0;
+ int chan;
+
+ for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
+ /* Unmask error interrupt */
+ out_le32(&sata_dma_regs->interrupt_mask.error.low,
+ DMA_ENABLE_CHAN(chan));
+
+ /* Unmask end-of-transfer interrupt */
+ out_le32(&sata_dma_regs->interrupt_mask.tfr.low,
+ DMA_ENABLE_CHAN(chan));
+ }
+
+ retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
+ if (retval) {
+ dev_err(dwc_dev, "%s: could not get IRQ %d\n", __func__, irq);
+ return -ENODEV;
+ }
+
+ /* Mark this interrupt as requested */
+ hsdev->irq_dma = irq;
+
+ return 0;
+}
+
+/*
+ * Function: map_sg_to_lli
+ * arguments: sg: scatter/gather list(sg)
+ * num_elems: no of elements in sg list
+ * dma_lli: LLI table
+ * dest: destination address
+ * read: whether the transfer is read or write
+ * returns array of AHB DMA Linked List Items
+ * This function creates a list of LLIs for DMA Xfr and returns the number
+ * of elements in the DMA linked list.
+ *
+ * Note that the Synopsis driver has a comment proposing that better performance
+ * is possible by only enabling interrupts on the last item in the linked list.
+ * However, it seems that could be a problem if an error happened on one of the
+ * first items. The transfer would halt, but no error interrupt would occur.
+ *
+ * Currently this function sets interrupts enabled for each linked list item:
+ * DMA_CTL_INT_EN.
+ */
+static int map_sg_to_lli(struct scatterlist *sg, int num_elems, struct lli *lli,
+ dma_addr_t dma_lli, void __iomem *dmadr_addr, int dir)
+{
+ int i, idx = 0;
+ int fis_len = 0;
+ dma_addr_t next_llp;
+ int bl;
+ unsigned int dma_ts = 0;
+
+ dev_dbg(dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x "
+ "dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
+ (u32)dmadr_addr);
+
+ bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
+
+ for (i = 0; i < num_elems; i++, sg++) {
+ u32 addr, offset;
+ u32 sg_len, len;
+
+ addr = (u32) sg_dma_address(sg);
+ sg_len = sg_dma_len(sg);
+
+ dev_dbg(dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len=%d\n",
+ __func__, i, addr, sg_len);
+
+ while (sg_len) {
+
+ if (idx >= SATA_DWC_DMAC_LLI_NUM) {
+ /* The LLI table is not large enough. */
+ dev_err(dwc_dev, "LLI table overrun (idx=%d)\n",
+ idx);
+ break;
+ }
+ len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
+ SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
+
+ offset = addr & 0xffff;
+ if ((offset + sg_len) > 0x10000)
+ len = 0x10000 - offset;
+
+ /*
+ * Make sure a LLI block is not created that will span a
+ * 8K max FIS boundary. If the block spans such a FIS
+ * boundary, there is a chance that a DMA burst will
+ * cross that boundary -- this results in an error in
+ * the host controller.
+ */
+ if (fis_len + len > 8192) {
+ dev_dbg(dwc_dev, "SPLITTING: fis_len=%d(0x%x) "
+ "len=%d(0x%x)\n", fis_len, fis_len,
+ len, len);
+ len = 8192 - fis_len;
+ fis_len = 0;
+ } else {
+ fis_len += len;
+ }
+ if (fis_len == 8192)
+ fis_len = 0;
+
+ /*
+ * Set DMA addresses and lower half of control register
+ * based on direction.
+ */
+ if (dir == DMA_FROM_DEVICE) {
+ lli[idx].dar = cpu_to_le32(addr);
+ lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
+
+ lli[idx].ctl.low = cpu_to_le32(
+ DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
+ DMA_CTL_SMS(0) |
+ DMA_CTL_DMS(1) |
+ DMA_CTL_SRC_MSIZE(bl) |
+ DMA_CTL_DST_MSIZE(bl) |
+ DMA_CTL_SINC_NOCHANGE |
+ DMA_CTL_SRC_TRWID(2) |
+ DMA_CTL_DST_TRWID(2) |
+ DMA_CTL_INT_EN |
+ DMA_CTL_LLP_SRCEN |
+ DMA_CTL_LLP_DSTEN);
+ } else { /* DMA_TO_DEVICE */
+ lli[idx].sar = cpu_to_le32(addr);
+ lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
+
+ lli[idx].ctl.low = cpu_to_le32(
+ DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
+ DMA_CTL_SMS(1) |
+ DMA_CTL_DMS(0) |
+ DMA_CTL_SRC_MSIZE(bl) |
+ DMA_CTL_DST_MSIZE(bl) |
+ DMA_CTL_DINC_NOCHANGE |
+ DMA_CTL_SRC_TRWID(2) |
+ DMA_CTL_DST_TRWID(2) |
+ DMA_CTL_INT_EN |
+ DMA_CTL_LLP_SRCEN |
+ DMA_CTL_LLP_DSTEN);
+ }
+
+ dev_dbg(dwc_dev, "%s setting ctl.high len: 0x%08x val: "
+ "0x%08x\n", __func__, len,
+ DMA_CTL_BLK_TS(len / 4));
+
+ /* Program the LLI CTL high register */
+ dma_ts = DMA_CTL_BLK_TS(len / 4);
+ lli[idx].ctl.high = cpu_to_le32(dma_ts);
+
+ /*
+ *Program the next pointer. The next pointer must be
+ * the physical address, not the virtual address.
+ */
+ next_llp = (dma_lli + ((idx + 1) * sizeof(struct lli)));
+
+ /* The last 2 bits encode the list master select. */
+ next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
+
+ lli[idx].llp = cpu_to_le32(next_llp);
+
+ idx++;
+ sg_len -= len;
+ addr += len;
+ }
+ }
+
+ /*
+ * The last next ptr has to be zero and the last control low register
+ * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
+ * and destination enable) set back to 0 (disabled.) This is what tells
+ * the core that this is the last item in the linked list.
+ */
+ if (idx) {
+ lli[idx-1].llp = 0x00000000;
+ lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
+
+ /* Flush cache to memory */
+ dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
+ DMA_BIDIRECTIONAL);
+ }
+
+ return idx;
+}
+
+/*
+ * Function: dma_dwc_xfer_start
+ * arguments: Channel number
+ * Return : None
+ * Enables the DMA channel
+ */
+static void dma_dwc_xfer_start(int dma_ch)
+{
+ /* Enable the DMA channel */
+ out_le32(&(sata_dma_regs->dma_chan_en.low),
+ in_le32(&(sata_dma_regs->dma_chan_en.low)) |
+ DMA_ENABLE_CHAN(dma_ch));
+}
+
+static int dma_dwc_channel_enabled(int ch)
+{
+ if (in_le32(&(sata_dma_regs->dma_chan_en.low)) & DMA_CHANNEL(ch))
+ return 1;
+
+ return 0;
+}
+
+static void dma_dwc_terminate_dma(int dma_ch)
+{
+ int enabled = dma_dwc_channel_enabled(dma_ch);
+
+ dev_info(dwc_dev, "%s terminate DMA on channel=%d enabled=%d\n",
+ __func__, dma_ch, enabled);
+
+ if (enabled) {
+ out_le32(&(sata_dma_regs->dma_chan_en.low),
+ DMA_DISABLE_CHAN(dma_ch));
+
+ do {
+ enabled = dma_dwc_channel_enabled(dma_ch);
+ } while (enabled);
+ }
+}
+
+static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
+ struct lli *lli, dma_addr_t dma_lli,
+ void __iomem *addr, int dir)
+{
+ int dma_ch;
+ int num_lli;
+
+ /* Acquire DMA channel */
+ dma_ch = dma_request_channel();
+ if (dma_ch == -1) {
+ dev_err(dwc_dev, "%s: dma channel unavailable\n", __func__);
+ return -EAGAIN;
+ }
+
+ /* Convert SG list to linked list of items (LLIs) for AHB DMA */
+ num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
+
+ dev_dbg(dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli: 0x%0xlx addr:"
+ " %p lli count: %d\n", __func__, sg, num_elems, lli,
+ (u32)dma_lli, addr, num_lli);
+
+ /* Clear channel interrupts */
+ clear_chan_interrupts(dma_ch);
+
+ /* Program the CFG register. */
+ out_le32(&(sata_dma_regs->chan_regs[dma_ch].cfg.high),
+ DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
+ out_le32(&(sata_dma_regs->chan_regs[dma_ch].cfg.low), 0);
+
+ /* Program the address of the linked list */
+ out_le32(&(sata_dma_regs->chan_regs[dma_ch].llp.low),
+ DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
+
+ /* Program the CTL register with src enable / dst enable */
+ out_le32(&(sata_dma_regs->chan_regs[dma_ch].ctl.low),
+ DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
+
+ return 0;
+}
+
+/*
+ * Function: dma_dwc_exit
+ * arguments: None
+ * returns status
+ * This function exits the SATA DMA driver
+ */
+static void dma_dwc_exit(struct sata_dwc_device *hsdev)
+{
+ dev_dbg(dwc_dev, "%s:\n", __func__);
+ if (sata_dma_regs)
+ iounmap(sata_dma_regs);
+
+ if (hsdev->irq_dma)
+ free_irq(hsdev->irq_dma, hsdev);
+}
+
+/*
+ * Function: dma_dwc_init
+ * arguments: hsdev
+ * returns status
+ * This function initializes the SATA DMA driver
+ */
+static int dma_dwc_init(struct sata_dwc_device *hsdev, struct resource *res,
+ int irq)
+{
+ int err;
+
+ sata_dma_regs = ioremap(res->start, res->end - res->start + 1);
+ if (!sata_dma_regs) {
+ dev_err(dwc_dev, "%s: ioremap failed\n", __func__);
+ err = -ENODEV;
+ goto error_out;
+ }
+
+ err = dma_request_interrupts(hsdev, irq);
+ if (err) {
+ dev_err(dwc_dev, "%s: dma_request_interrupts returns %d\n",
+ __func__, err);
+ goto error_out;
+ }
+
+ /* Enabe DMA */
+ out_le32(&(sata_dma_regs->dma_cfg.low), DMA_EN);
+
+ dev_notice(dwc_dev, "DMA initialized\n");
+ dev_dbg(dwc_dev, "SATA DMA registers=0x%p\n", sata_dma_regs);
+
+ return 0;
+
+error_out:
+ dma_dwc_exit(hsdev);
+
+ return err;
+}
+
+static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
+{
+ if (scr > SCR_NOTIFICATION) {
+ dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
+ __func__, scr);
+ return -EINVAL;
+ }
+
+ *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4));
+ dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
+ __func__, link->ap->print_id, scr, *val);
+
+ return 0;
+}
+
+static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
+{
+ dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
+ __func__, link->ap->print_id, scr, val);
+ if (scr > SCR_NOTIFICATION) {
+ dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
+ __func__, scr);
+ return -EINVAL;
+ }
+ out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val);
+
+ return 0;
+}
+
+static inline u32 core_scr_read(unsigned int scr)
+{
+ return in_le32((void __iomem *)scr_addr_sstatus + (scr * 4));
+}
+
+static inline void core_scr_write(unsigned int scr, u32 val)
+{
+ out_le32((void __iomem *)scr_addr_sstatus + (scr * 4), val);
+}
+
+static inline void clear_serror(void)
+{
+ out_le32((void __iomem *)scr_addr_sstatus + 4,
+ in_le32((void __iomem *)scr_addr_sstatus + 4));
+}
+
+static inline void clear_intpr(struct sata_dwc_device *hsdev)
+{
+ out_le32(&hsdev->sata_dwc_regs->intpr,
+ in_le32(&hsdev->sata_dwc_regs->intpr));
+}
+
+static inline void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
+{
+ out_le32(&hsdev->sata_dwc_regs->intpr,
+ in_le32(&hsdev->sata_dwc_regs->intpr));
+}
+
+static inline void disable_err_irq(struct sata_dwc_device *hsdev)
+{
+ out_le32(&hsdev->sata_dwc_regs->intmr,
+ in_le32(&hsdev->sata_dwc_regs->intmr) & ~SATA_DWC_INTMR_ERRM);
+ out_le32(&hsdev->sata_dwc_regs->errmr, ~SATA_DWC_SERROR_ERR_BITS);
+}
+
+static inline void enable_err_irq(struct sata_dwc_device *hsdev)
+{
+ out_le32(&hsdev->sata_dwc_regs->intmr,
+ in_le32(&hsdev->sata_dwc_regs->intmr) | SATA_DWC_INTMR_ERRM);
+ out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
+}
+
+static inline u32 qcmd_tag_to_mask(u8 tag)
+{
+ return 0x00000001 << (tag & 0x1f);
+}
+
+/* See ahci.c */
+static void sata_dwc_error_intr(struct ata_port *ap,
+ struct sata_dwc_device *hsdev, uint intpr)
+{
+ struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+ struct ata_eh_info *ehi = &ap->link.eh_info;
+ unsigned int err_mask = 0, action = 0;
+ struct ata_queued_cmd *qc;
+ u32 serror;
+ u8 status, tag;
+ u32 err_reg;
+
+ ata_ehi_clear_desc(ehi);
+
+ serror = core_scr_read(SCR_ERROR);
+ status = ap->ops->sff_check_status(ap);
+
+ err_reg = in_le32(&(sata_dma_regs->interrupt_status.error.low));
+ tag = ap->link.active_tag;
+
+ dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
+ "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
+ __func__, serror, intpr, status, dma_interrupt_count,
+ hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
+
+ /* Clear error register and interrupt bit */
+ clear_serror();
+ clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
+
+ /* This is the only error happening now. */
+ /* TODO check for exact error */
+ err_mask |= AC_ERR_HOST_BUS;
+ action |= ATA_EH_RESET;
+
+ /* Pass this on to EH */
+ ehi->serror |= serror;
+ ehi->action |= action;
+
+ qc = ata_qc_from_tag(ap, tag);
+ if (qc)
+ qc->err_mask |= err_mask;
+ else
+ ehi->err_mask |= err_mask;
+
+ ata_port_abort(ap);
+
+ /*
+ if (irq_stat & PORT_IRQ_FREEZE)
+ ata_port_freeze(ap);
+ else
+ ata_port_abort(ap);
+ */
+}
+
+/*
+ * Function : sata_dwc_isr
+ * arguments : irq, void *dev_instance, struct pt_regs *regs
+ * Return value : irqreturn_t - status of IRQ
+ * This Interrupt handler called via port ops registered function.
+ * .irq_handler = sata_dwc_isr
+ */
+static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
+{
+ struct ata_host *host = (struct ata_host *)dev_instance;
+ struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
+ struct ata_port *ap;
+ struct ata_queued_cmd *qc;
+ unsigned long flags;
+ u8 status, tag;
+ int handled, num_processed, port = 0;
+ uint intpr, sactive, sactive2, tag_mask;
+ struct sata_dwc_device_port *hsdevp;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ /* Read the interrupt register */
+ intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
+
+ ap = host->ports[port];
+ hsdevp = HSDEVP_FROM_AP(ap);
+
+ dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
+ ap->link.active_tag);
+
+ /* Check for error interrupt */
+ if (intpr & SATA_DWC_INTPR_ERR) {
+ sata_dwc_error_intr(ap, hsdev, intpr);
+ handled = 1;
+ goto done_irqrestore;
+ }
+
+ /* Check for DMA SETUP FIS (FP DMA) interrupt */
+ if (intpr & SATA_DWC_INTPR_NEWFP) {
+ clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
+
+ tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
+ dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
+ if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
+ dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
+
+ sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
+
+ qc = ata_qc_from_tag(ap, tag);
+ /*
+ * Start FP DMA for NCQ command. At this point the tag is the
+ * active tag. It is the tag that matches the command about to
+ * be completed.
+ */
+ qc->ap->link.active_tag = tag;
+ sata_dwc_bmdma_start_by_tag(qc, tag);
+
+ handled = 1;
+ goto done_irqrestore;
+ }
+
+ sactive = core_scr_read(SCR_ACTIVE);
+ tag_mask = (sata_dwc_sactive_issued | sactive) ^ sactive;
+
+ /* If no sactive issued and tag_mask is zero then this is not NCQ */
+ if (sata_dwc_sactive_issued == 0 && tag_mask == 0) {
+ tag = 0;
+ qc = ata_qc_from_tag(ap, tag);
+
+ /* DEV interrupt w/ no active qc? */
+ if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
+ dev_err(ap->dev, "%s intr with no active qc qc=%p\n",
+ __func__, qc);
+ ata_sff_check_status(ap);
+ handled = 1;
+ goto done_irqrestore;
+ }
+
+ status = ap->ops->sff_check_status(ap);
+
+ qc->ap->link.active_tag = tag;
+ hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
+
+ if (status & ATA_ERR) {
+ dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
+ sata_dwc_qc_complete(ap, qc, 1);
+ handled = 1;
+ goto done_irqrestore;
+ }
+
+ dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
+ __func__, prot_2_txt(qc->tf.protocol));
+drv_still_busy:
+ if (ata_is_dma(qc->tf.protocol)) {
+ int dma_flag = hsdevp->dma_pending[tag];
+ /*
+ * Each DMA transaction produces 2 interrupts. The DMAC
+ * transfer complete interrupt and the SATA controller
+ * operation done interrupt. The command should be
+ * completed only after both interrupts are seen.
+ */
+ dma_interrupt_count++;
+ if (dma_flag == SATA_DWC_DMA_PEND_NONE) {
+ dev_err(ap->dev, "%s: DMA not pending "
+ "intpr=0x%08x status=0x%08x pend=%d\n",
+ __func__, intpr, status, dma_flag);
+ }
+
+ if ((dma_interrupt_count % 2) == 0)
+ sata_dwc_dma_xfer_complete(ap, 1);
+ } else {
+ if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
+ goto drv_still_busy;
+ }
+
+ handled = 1;
+ goto done_irqrestore;
+ }
+
+ /*
+ * This is a NCQ command. At this point we need to figure out for which
+ * tags we have gotten a completion interrupt. One interrupt may serve
+ * as completion for more than one operation when commands are queued
+ * (NCQ). We need to process each completed command.
+ */
+
+process_cmd: /* process completed commands */
+ sactive = core_scr_read(SCR_ACTIVE);
+ tag_mask = (sata_dwc_sactive_issued | sactive) ^ sactive;
+
+ if (sactive != 0 || sata_dwc_sactive_issued > 1 || tag_mask > 1) {
+ dev_dbg(ap->dev, "%s NCQ: sactive=0x%08x sactive_issued=0x%08x"
+ " tag_mask=0x%08x\n", __func__, sactive,
+ sata_dwc_sactive_issued, tag_mask);
+ }
+
+ if ((tag_mask | sata_dwc_sactive_issued) != sata_dwc_sactive_issued) {
+ dev_warn(ap->dev, "Bad tag mask? sactive=0x%08x "
+ "sata_dwc_sactive_issued=0x%08x tag_mask=0x%08x\n",
+ sactive, sata_dwc_sactive_issued, tag_mask);
+ }
+
+ /* read just to clear ... not bad if currently still busy */
+ status = ap->ops->sff_check_status(ap);
+ dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
+
+ tag = 0;
+ num_processed = 0;
+ while (tag_mask) {
+ num_processed++;
+ while (!(tag_mask & 0x00000001)) {
+ tag++;
+ tag_mask <<= 1;
+ }
+ tag_mask &= (~0x00000001);
+ qc = ata_qc_from_tag(ap, tag);
+
+ /* To be picked up by completion functions */
+ qc->ap->link.active_tag = tag;
+ hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
+
+ /* Let libata/scsi layers handle error */
+ if (status & ATA_ERR) {
+ dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n",
+ __func__, status);
+
+ sata_dwc_qc_complete(ap, qc, 1);
+ handled = 1;
+ goto done_irqrestore;
+ }
+
+ /* Process completed command */
+ dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
+ prot_2_txt(qc->tf.protocol));
+ if (ata_is_dma(qc->tf.protocol)) {
+ dma_interrupt_count++;
+ if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PEND_NONE)
+ dev_warn(ap->dev,
+ "%s: DMA not pending?\n", __func__);
+ if ((dma_interrupt_count % 2) == 0)
+ sata_dwc_dma_xfer_complete(ap, 1);
+ } else {
+ if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
+ goto still_busy;
+ }
+ continue;
+
+still_busy:
+ ap->stats.idle_irq++;
+ dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
+ ap->print_id);
+ } /* while tag_mask */
+
+ /*
+ * Check to see if any commands completed while we were processing our
+ * initial set of completed commands (reading of status clears
+ * interrupts, so we might miss a completed command interrupt if one
+ * came in while we were processing:
+ * we read status as part of processing a completed command).
+ */
+ sactive2 = core_scr_read(SCR_ACTIVE);
+ if (sactive2 != sactive) {
+ dev_dbg(ap->dev, "More finished - sactive=0x%x sactive2=0x%x\n",
+ sactive, sactive2);
+ goto process_cmd;
+ }
+ handled = 1;
+
+done_irqrestore:
+ spin_unlock_irqrestore(&host->lock, flags);
+ return IRQ_RETVAL(handled);
+}
+
+static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
+{
+ struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
+
+ if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PEND_RX) {
+ out_le32(&(hsdev->sata_dwc_regs->dmacr),
+ SATA_DWC_DMACR_RX_CLEAR(
+ in_le32(&(hsdev->sata_dwc_regs->dmacr))));
+ } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PEND_TX) {
+ out_le32(&(hsdev->sata_dwc_regs->dmacr),
+ SATA_DWC_DMACR_TX_CLEAR(
+ in_le32(&(hsdev->sata_dwc_regs->dmacr))));
+ } else {
+ /*
+ * This should not happen, it indicates the driver is out of
+ * sync. If it does happen, clear dmacr anyway.
+ */
+ dev_err(dwc_dev, "%s DMA protocol RX and TX DMA not pending "
+ "tag=0x%02x pending=%d dmacr: 0x%08x\n",
+ __func__, tag, hsdevp->dma_pending[tag],
+ in_le32(&(hsdev->sata_dwc_regs->dmacr)));
+ out_le32(&(hsdev->sata_dwc_regs->dmacr),
+ SATA_DWC_DMACR_TXRXCH_CLEAR);
+ }
+}
+
+static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
+{
+ struct ata_queued_cmd *qc;
+ struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+ struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
+ u8 tag = 0;
+
+ tag = ap->link.active_tag;
+ qc = ata_qc_from_tag(ap, tag);
+
+#ifdef DEBUG_NCQ
+ if (tag > 0) {
+ dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
+ "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
+ dir_2_txt(qc->dma_dir), prot_2_txt(qc->tf.protocol),
+ in_le32(&(hsdev->sata_dwc_regs->dmacr)));
+ }
+#endif
+
+ if (ata_is_dma(qc->tf.protocol)) {
+ if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PEND_NONE) {
+ dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
+ "pending dmacr: 0x%08x\n", __func__,
+ in_le32(&(hsdev->sata_dwc_regs->dmacr)));
+ }
+
+ hsdevp->dma_pending[tag] = SATA_DWC_DMA_PEND_NONE;
+ sata_dwc_qc_complete(ap, qc, check_status);
+ ap->link.active_tag = ATA_TAG_POISON;
+ } else {
+ sata_dwc_qc_complete(ap, qc, check_status);
+ }
+}
+
+static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
+ u32 check_status)
+{
+ u8 status = 0;
+ int i = 0;
+ u32 mask = 0x0;
+ u8 tag = qc->tag;
+ struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+ u32 serror;
+
+ dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
+
+ if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PEND_TX)
+ dev_err(ap->dev, "TX DMA PENDING\n");
+ else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PEND_RX)
+ dev_err(ap->dev, "RX DMA PENDING\n");
+
+ if (check_status) {
+ i = 0;
+ do {
+ /* check main status, clearing INTRQ */
+ status = ap->ops->sff_check_status(ap);
+ if (status & ATA_BUSY) {
+ dev_dbg(ap->dev, "STATUS BUSY (0x%02x) [%d]\n",
+ status, i);
+ }
+ if (++i > 10)
+ break;
+ } while (status & ATA_BUSY);
+
+ status = ap->ops->sff_check_status(ap);
+ if (unlikely(status & ATA_BUSY))
+ dev_err(ap->dev, "QC complete cmd=0x%02x STATUS BUSY "
+ "(0x%02x) [%d]\n", qc->tf.command, status, i);
+ serror = core_scr_read(SCR_ERROR);
+ if (serror & SATA_DWC_SERROR_ERR_BITS)
+ dev_err(ap->dev, "****** SERROR=0x%08x ******\n",
+ serror);
+ }
+ dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u: "
+ "protocol=%d\n", qc->tf.command, status, ap->print_id,
+ qc->tf.protocol);
+
+ /* clear active bit */
+ mask = (~(qcmd_tag_to_mask(tag)));
+ sata_dwc_sactive_queued = sata_dwc_sactive_queued & mask;
+ sata_dwc_sactive_issued = sata_dwc_sactive_issued & mask;
+
+ /* Complete taskfile transaction (does not read SCR registers) */
+ ata_qc_complete(qc);
+
+ return 0;
+}
+
+static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
+{
+ /* Enable selective interrupts by setting the interrupt mask register */
+ out_le32(&hsdev->sata_dwc_regs->intmr,
+ SATA_DWC_INTMR_ERRM |
+ SATA_DWC_INTMR_NEWFPM |
+ SATA_DWC_INTMR_PMABRTM |
+ SATA_DWC_INTMR_DMATM);
+
+ /*
+ * Unmask the error bits that should trigger an error interrupt by
+ * setting the error mask register.
+ */
+ out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
+
+ dev_dbg(dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n", __func__,
+ in_le32(&hsdev->sata_dwc_regs->intmr),
+ in_le32(&hsdev->sata_dwc_regs->errmr));
+}
+
+static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
+{
+ port->cmd_addr = (void *)base + 0x00;
+ port->data_addr = (void *)base + 0x00;
+
+ port->error_addr = (void *)base + 0x04;
+ port->feature_addr = (void *)base + 0x04;
+
+ port->nsect_addr = (void *)base + 0x08;
+
+ port->lbal_addr = (void *)base + 0x0c;
+ port->lbam_addr = (void *)base + 0x10;
+ port->lbah_addr = (void *)base + 0x14;
+
+ port->device_addr = (void *)base + 0x18;
+ port->command_addr = (void *)base + 0x1c;
+ port->status_addr = (void *)base + 0x1c;
+
+ port->altstatus_addr = (void *)base + 0x20;
+ port->ctl_addr = (void *)base + 0x20;
+}
+
+/*
+ * Function : sata_dwc_port_start
+ * arguments : struct ata_ioports *port
+ * Return value : returns 0 if success, error code otherwise
+ * This function allocates the scatter gather LLI table for AHB DMA
+ */
+static int sata_dwc_port_start(struct ata_port *ap)
+{
+ int err = 0;
+ struct sata_dwc_device *hsdev;
+ struct sata_dwc_device_port *hsdevp = NULL;
+ struct device *pdev;
+ u32 sstatus;
+ int i;
+
+ hsdev = HSDEV_FROM_AP(ap);
+
+ dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
+
+ hsdev->host = ap->host;
+ pdev = ap->host->dev;
+ if (!pdev) {
+ dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
+ err = -ENODEV;
+ goto cleanup_exit;
+ }
+
+ /* Allocate Port Struct */
+ hsdevp = kmalloc(sizeof(*hsdevp), GFP_KERNEL);
+ if (!hsdevp) {
+ dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
+ err = -ENOMEM;
+ goto cleanup_exit;
+ }
+ memset(hsdevp, 0, sizeof(*hsdevp));
+ hsdevp->hsdev = hsdev;
+
+ for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
+ hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
+
+ ap->prd = 0; /* set these so libata doesn't use them */
+ ap->prd_dma = 0;
+
+ /*
+ * DMA - Assign scatter gather LLI table. We can't use the libata
+ * version since it's PRD is IDE PCI specific.
+ */
+ for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
+ hsdevp->llit[i] = dma_alloc_coherent(pdev,
+ SATA_DWC_DMAC_LLI_TBL_SZ,
+ &(hsdevp->llit_dma[i]),
+ GFP_ATOMIC);
+ if (!hsdevp->llit[i]) {
+ dev_err(ap->dev, "%s: dma_alloc_coherent failed size "
+ "0x%x\n", __func__, SATA_DWC_DMAC_LLI_TBL_SZ);
+ err = -ENOMEM;
+ goto cleanup_exit;
+ }
+ }
+
+ if (ap->port_no == 0) {
+ dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
+ __func__);
+
+ out_le32(&hsdev->sata_dwc_regs->dmacr,
+ SATA_DWC_DMACR_TXRXCH_CLEAR);
+
+ dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n", __func__);
+ out_le32(&hsdev->sata_dwc_regs->dbtsr,
+ (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
+ SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
+ }
+
+ /* Clear any error bits before libata starts issuing commands */
+ clear_serror();
+
+ ap->private_data = hsdevp;
+
+ /* Are we in Gen I or II */
+ sstatus = core_scr_read(SCR_STATUS);
+ switch (SATA_DWC_SCR0_SPD_GET(sstatus)) {
+ case 0x0:
+ dev_info(ap->dev, "**** No neg speed (nothing attached?) \n");
+ break;
+ case 0x1:
+ dev_info(ap->dev, "**** GEN I speed rate negotiated \n");
+ break;
+ case 0x2:
+ dev_info(ap->dev, "**** GEN II speed rate negotiated \n");
+ break;
+ }
+
+cleanup_exit:
+ if (err) {
+ kfree(hsdevp);
+ sata_dwc_port_stop(ap);
+ dev_dbg(ap->dev, "%s: fail\n", __func__);
+ } else {
+ dev_dbg(ap->dev, "%s: done\n", __func__);
+ }
+
+ return err;
+}
+
+static void sata_dwc_port_stop(struct ata_port *ap)
+{
+ int i;
+ struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
+ struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+
+ dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
+
+ if (hsdevp && hsdev) {
+ /* deallocate LLI table */
+ for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
+ dma_free_coherent(ap->host->dev,
+ SATA_DWC_DMAC_LLI_TBL_SZ,
+ hsdevp->llit[i], hsdevp->llit_dma[i]);
+ }
+
+ kfree(hsdevp);
+ }
+ ap->private_data = NULL;
+}
+
+/*
+ * Function : sata_dwc_exec_command_by_tag
+ * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
+ * Return value : None
+ * This function keeps track of individual command tag ids and calls
+ * ata_exec_command in libata
+ */
+static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
+ struct ata_taskfile *tf,
+ u8 tag, u32 cmd_issued)
+{
+ unsigned long flags;
+ struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+
+ dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
+ ata_cmd_2_txt(tf), tag);
+
+ spin_lock_irqsave(&ap->host->lock, flags);
+ hsdevp->cmd_issued[tag] = cmd_issued;
+ spin_unlock_irqrestore(&ap->host->lock, flags);
+
+ /*
+ * Clear SError before executing a new command.
+ *
+ * TODO if we read a PM's registers now, we will throw away the task
+ * file values loaded into the shadow registers for this command.
+ *
+ * sata_dwc_scr_write and read can not be used here. Clearing the PM
+ * managed SError register for the disk needs to be done before the
+ * task file is loaded.
+ */
+ clear_serror();
+ ata_sff_exec_command(ap, tf);
+}
+
+static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
+{
+ sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
+ SATA_DWC_CMD_ISSUED_PEND);
+}
+
+static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
+{
+ u8 tag = qc->tag;
+
+ if (ata_is_ncq(qc->tf.protocol)) {
+ dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
+ __func__, qc->ap->link.sactive, tag);
+ } else {
+ tag = 0;
+ }
+
+ sata_dwc_bmdma_setup_by_tag(qc, tag);
+}
+
+static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
+{
+ int start_dma;
+ u32 reg, dma_chan;
+ struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
+ struct ata_port *ap = qc->ap;
+ struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+ int dir = qc->dma_dir;
+ dma_chan = hsdevp->dma_chan[tag];
+
+ /* Used for ata_bmdma_start(qc) -- we are not BMDMA compatible */
+
+ if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
+ start_dma = 1;
+ if (dir == DMA_TO_DEVICE)
+ hsdevp->dma_pending[tag] = SATA_DWC_DMA_PEND_TX;
+ else
+ hsdevp->dma_pending[tag] = SATA_DWC_DMA_PEND_RX;
+ } else {
+ dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
+ "(tag=%d) - DMA NOT started\n", __func__,
+ hsdevp->cmd_issued[tag], tag);
+ start_dma = 0;
+ }
+
+ dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
+ "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
+ dir_2_txt(qc->dma_dir), start_dma);
+ sata_dwc_tf_dump(&(qc->tf));
+
+ if (start_dma) {
+ reg = core_scr_read(SCR_ERROR);
+ if (reg & SATA_DWC_SERROR_ERR_BITS) {
+ dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
+ __func__, reg);
+ }
+
+ if (dir == DMA_TO_DEVICE)
+ out_le32(&hsdev->sata_dwc_regs->dmacr,
+ SATA_DWC_DMACR_TXCHEN);
+ else
+ out_le32(&hsdev->sata_dwc_regs->dmacr,
+ SATA_DWC_DMACR_RXCHEN);
+
+ /* Enable AHB DMA transfer on the specified channel */
+ dma_dwc_xfer_start(dma_chan);
+ }
+}
+
+static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
+{
+ u8 tag = qc->tag;
+
+ if (ata_is_ncq(qc->tf.protocol)) {
+ dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
+ __func__, qc->ap->link.sactive, tag);
+ } else {
+ tag = 0;
+ }
+
+ dev_dbg(qc->ap->dev, "%s\n", __func__);
+ sata_dwc_bmdma_start_by_tag(qc, tag);
+}
+
+/*
+ * Function : sata_dwc_qc_prep_by_tag
+ * arguments : ata_queued_cmd *qc, u8 tag
+ * Return value : None
+ * qc_prep for a particular queued command based on tag
+ */
+static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
+{
+ struct scatterlist *sg = qc->sg;
+ struct ata_port *ap = qc->ap;
+ u32 dma_chan;
+ struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
+ struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+ int dir;
+ int err;
+
+ dir = qc->dma_dir;
+
+ if ((dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
+ return;
+
+ dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
+ __func__, ap->port_no, dir_2_txt(dir), qc->n_elem);
+
+ dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
+ hsdevp->llit_dma[tag],
+ (void *__iomem)(&hsdev->sata_dwc_regs->dmadr),
+ dir);
+ if (dma_chan < 0) {
+ dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
+ __func__, err);
+ return;
+ }
+
+ hsdevp->dma_chan[tag] = dma_chan;
+}
+
+static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+
+#ifdef DEBUG_NCQ
+ if (qc->tag > 0 || ap->link.sactive > 1) {
+ dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s"
+ " ap active_tag=0x%08x ap sactive=0x%08x\n",
+ __func__, ap->print_id, qc->tf.command,
+ ata_cmd_2_txt(&qc->tf), qc->tag,
+ prot_2_txt(qc->tf.protocol), ap->link.active_tag,
+ ap->link.sactive);
+ }
+#endif
+
+ if (ata_is_ncq(qc->tf.protocol)) {
+ ap->ops->sff_tf_load(ap, &qc->tf);
+ sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
+ SATA_DWC_CMD_ISSUED_PEND);
+ } else {
+ ata_sff_qc_issue(qc);
+ }
+
+ return 0;
+}
+
+/*
+ * Function : sata_dwc_eng_timeout
+ * arguments : ata_port *ap
+ * Return value : None
+ * error handler for DMA time out
+ * ata_eng_timeout(ap) -- this does bmdma stuff which can not be done by this
+ * driver. SEE ALSO ata_qc_timeout(ap)
+ */
+static void sata_dwc_eng_timeout(struct ata_port *ap)
+{
+ struct ata_queued_cmd *qc;
+ struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
+ struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
+ u8 tag;
+ uint mask = 0x0;
+ unsigned long flags;
+ u32 serror, intpr, dma_ch;
+
+ tag = ap->link.active_tag;
+ dma_ch = hsdevp->dma_chan[tag];
+ qc = ata_qc_from_tag(ap, tag);
+
+ dev_err(ap->dev, "%s: id=%d active_tag=%d qc=%p dma_chan=%d\n",
+ __func__, ap->print_id, tag, qc, dma_ch);
+
+ if (!qc) {
+ dev_err(ap->dev,
+ "%s: timeout without queued command\n", __func__);
+ return;
+ }
+
+ intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
+ serror = core_scr_read(SCR_ERROR);
+
+ dev_err(ap->dev, "intpr=0x%08x serror=0x%08x\n", intpr, serror);
+
+ /* If there are no error bits set, can we just pass this on to eh? */
+ if (!(serror & SATA_DWC_SERROR_ERR_BITS) &&
+ !(intpr & SATA_DWC_INTPR_ERR)) {
+
+ spin_lock_irqsave(&ap->host->lock, flags);
+ if (dma_dwc_channel_enabled(dma_ch))
+ dma_dwc_terminate_dma(dma_ch);
+
+ hsdevp->dma_pending[tag] = SATA_DWC_DMA_PEND_NONE;
+
+ /* clear active bit */
+ mask = (~(qcmd_tag_to_mask(tag)));
+ sata_dwc_sactive_queued = sata_dwc_sactive_queued & mask;
+ sata_dwc_sactive_issued = sata_dwc_sactive_issued & mask;
+
+ spin_unlock_irqrestore(&ap->host->lock, flags);
+ } else {
+ /* This is wrong, what really needs to be done is a reset. */
+
+ spin_lock_irqsave(ap->lock, flags);
+
+ if (ata_is_dma(qc->tf.protocol)) {
+ /* disable DMAC */
+ dma_dwc_terminate_dma(dma_ch);
+ }
+
+ spin_unlock_irqrestore(ap->lock, flags);
+ }
+
+ WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
+ if (qc->flags & ATA_QCFLAG_ACTIVE) {
+ qc->err_mask |= AC_ERR_TIMEOUT;
+ /*
+ * test-only: The original code (AMCC: 2.6.19) called
+ * ata_eng_timeout(ap) here. This function is not available
+ * anymore. So what to do now?
+ */
+ }
+}
+
+/*
+ * Function : sata_dwc_qc_prep
+ * arguments : ata_queued_cmd *qc
+ * Return value : None
+ * qc_prep for a particular queued command
+ */
+static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
+{
+ u32 sactive;
+ u8 tag = qc->tag;
+
+#ifdef DEBUG_NCQ
+ if (qc->tag > 0) {
+ dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
+ __func__, tag, qc->ap->link.active_tag);
+ }
+#endif
+
+ if (qc->tf.protocol == ATA_PROT_NCQ) {
+ sactive = core_scr_read(SCR_ACTIVE);
+ sactive |= (0x00000001 << tag);
+ core_scr_write(SCR_ACTIVE, sactive);
+ dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
+ "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
+ sactive);
+ } else {
+ tag = 0;
+ }
+
+ sata_dwc_qc_prep_by_tag(qc, tag);
+}
+
+/*
+ * test-only: Needed when no drive is connected upon driver startup.
+ * Otherwise, by using the default prereset routine, the driver crashes
+ * upon loading.
+ * Not sure if this could be handled differently.
+ */
+static int sata_dwc_prereset(struct ata_link *link, unsigned long deadline)
+{
+ struct ata_port *ap = link->ap;
+ struct ata_eh_context *ehc = &ap->link.eh_context;
+ int rc = 0;
+
+ if (ata_link_online(link)) {
+ rc = ata_sff_wait_ready(link, deadline);
+ } else {
+ /* tell EH to bail */
+ ehc->i.action &= ~ATA_EH_RESET;
+ }
+
+ return rc;
+}
+
+/*
+ * scsi mid-layer and libata interface structures
+ */
+static struct scsi_host_template sata_dwc_sht = {
+ ATA_NCQ_SHT(DRV_NAME),
+ /*
+ * test-only: Currently this driver doesn't handle NCQ
+ * correctly. We enable NCQ but set the queue depth to a
+ * max of 1. This will get fixed in in a future release.
+ */
+ .can_queue = ATA_DEF_QUEUE, /* ATA_MAX_QUEUE */
+ .dma_boundary = ATA_DMA_BOUNDARY,
+};
+
+static struct ata_port_operations sata_dwc_ops = {
+ .inherits = &ata_sff_port_ops,
+
+ .qc_prep = sata_dwc_qc_prep,
+ .qc_issue = sata_dwc_qc_issue,
+
+ .scr_read = sata_dwc_scr_read,
+ .scr_write = sata_dwc_scr_write,
+
+ .port_start = sata_dwc_port_start,
+ .port_stop = sata_dwc_port_stop,
+
+ .bmdma_setup = sata_dwc_bmdma_setup,
+ .bmdma_start = sata_dwc_bmdma_start,
+
+ .prereset = sata_dwc_prereset,
+
+ /* test-only: really needed? */
+ .eng_timeout = sata_dwc_eng_timeout,
+};
+
+static const struct ata_port_info sata_dwc_port_info[] = {
+ {
+ /*
+ * test-only: Currently this driver doesn't handle NCQ
+ * correctly. So we disable NCQ here for now. To enable
+ * it ATA_FLAG_NCQ needs to be added to the flags below.
+ */
+ .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+ ATA_FLAG_MMIO,
+ .pio_mask = 0x1f, /* pio 0-4 */
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &sata_dwc_ops,
+ },
+};
+
+static int sata_dwc_probe(struct platform_device *pdev)
+{
+ struct sata_dwc_device *hsdev;
+ u32 idr, versionr;
+ char *ver = (char *)&versionr;
+ u8 *base = NULL;
+ int err = 0;
+ struct resource *res;
+ int irq;
+ struct ata_host *host;
+ struct ata_port_info pi = sata_dwc_port_info[0];
+ const struct ata_port_info *ppi[] = { &pi, NULL };
+
+
+ /* Allocate DWC SATA device */
+ hsdev = kmalloc(sizeof(*hsdev), GFP_KERNEL);
+ if (hsdev == NULL) {
+ dev_err(&pdev->dev, "kmalloc failed for hsdev\n");
+ err = -ENOMEM;
+ goto error_out;
+ }
+ memset(hsdev, 0, sizeof(*hsdev));
+
+ /* Get physical SATA register base address */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "no reg addr\n");
+ err = -ENODEV;
+ goto error_out;
+ }
+
+ /* Ioremap SATA registers */
+ base = ioremap(res->start, res->end - res->start + 1);
+ if (!base) {
+ dev_err(&pdev->dev, "ioremap failed for 0x%llx\n", res->start);
+ err = -ENODEV;
+ goto error_out;
+ }
+ hsdev->reg_base = base;
+ dev_dbg(&pdev->dev, "ioremap done (0x%llx -> 0x%08x)\n",
+ res->start, (u32)base);
+
+ /* Synopsys DWC SATA specific Registers */
+ hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
+
+ /* Allocate and fill host */
+ host = ata_host_alloc_pinfo(&pdev->dev, ppi, SATA_DWC_MAX_PORTS);
+ if (!host) {
+ dev_err(&pdev->dev, "ata_host_alloc_pinfo failed\n");
+ err = -ENOMEM;
+ goto error_out;
+ }
+
+ host->private_data = hsdev;
+
+ /* Setup port */
+ host->ports[0]->ioaddr.cmd_addr = base;
+ host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
+ scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
+ sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
+
+ /* Read the ID and Version Registers */
+ idr = in_le32(&hsdev->sata_dwc_regs->idr);
+ versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
+ dev_notice(&pdev->dev, "id %d, controller version %c.%c%c\n",
+ idr, ver[0], ver[1], ver[2]);
+
+ /* Get SATA DMA interrupt number */
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+ if (!res) {
+ dev_err(&pdev->dev, "no SATA DMA irq\n");
+ err = -ENODEV;
+ goto error_out;
+ }
+ irq = res->start;
+
+ /* Get physical SATA DMA register base address */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res) {
+ dev_err(&pdev->dev, "no reg addr\n");
+ err = -ENODEV;
+ goto error_out;
+ }
+
+ /* Save dev for later use in dev_xxx() routines */
+ dwc_dev = &pdev->dev;
+
+ /* Initialize AHB DMAC */
+ dma_dwc_init(hsdev, res, irq);
+
+ /* Enable SATA Interrupts */
+ sata_dwc_enable_interrupts(hsdev);
+
+ /* Get SATA interrupt number */
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "no SATA irq\n");
+ err = -ENODEV;
+ goto error_out;
+ }
+ irq = res->start;
+
+ /*
+ * Now, register with libATA core, this will also initiate the
+ * device discovery process, invoking our port_start() handler &
+ * error_handler() to execute a dummy Softreset EH session
+ */
+ ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
+
+ dev_set_drvdata(&pdev->dev, host);
+
+ /* Everything is fine */
+ return 0;
+
+error_out:
+ /* Free SATA DMA resources */
+ dma_dwc_exit(hsdev);
+
+ if (base)
+ iounmap(base);
+
+ kfree(hsdev);
+
+ return err;
+}
+
+static int sata_dwc_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ata_host *host = dev_get_drvdata(dev);
+ struct sata_dwc_device *hsdev = host->private_data;
+
+ ata_host_detach(host);
+
+ dev_set_drvdata(dev, NULL);
+
+ /* Free SATA DMA resources */
+ dma_dwc_exit(hsdev);
+
+ iounmap(hsdev->reg_base);
+ kfree(hsdev);
+ kfree(host);
+
+ dev_dbg(&pdev->dev, "done\n");
+
+ return 0;
+}
+
+static struct platform_driver sata_dwc_driver = {
+ .probe = sata_dwc_probe,
+ .remove = sata_dwc_remove,
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init sata_dwc_init(void)
+{
+ int err;
+
+ err = platform_driver_register(&sata_dwc_driver);
+
+ return err;
+}
+
+static void __exit sata_dwc_exit(void)
+{
+ platform_driver_unregister(&sata_dwc_driver);
+}
+
+module_init(sata_dwc_init);
+module_exit(sata_dwc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
+MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
+MODULE_VERSION(DRV_VERSION);
--
1.5.5
^ permalink raw reply related
* Re: [PATCH v6] introduce macro spin_event_timeout()
From: Timur Tabi @ 2009-05-01 20:55 UTC (permalink / raw)
To: Kumar Gala; +Cc: scottwood, linuxppc-dev
In-Reply-To: <D823E17E-3066-45D5-A33D-539FA0883B55@kernel.crashing.org>
Kumar Gala wrote:
> I wouldn't call it spin_event_timeout as its a bit too generic of a
> name for something that is arch specific.
Well, I'm hoping it won't be arch-specific forever. I'd like to see
other architectures implement something like tb_ticks_per_usec. I'm
only tackling PowerPC for now.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [PATCH v6] introduce macro spin_event_timeout()
From: Scott Wood @ 2009-05-01 20:56 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Timur Tabi
In-Reply-To: <D823E17E-3066-45D5-A33D-539FA0883B55@kernel.crashing.org>
Kumar Gala wrote:
> I wouldn't call it spin_event_timeout as its a bit too generic of a name
> for something that is arch specific.
The concept is not arch-specific -- ideally, other architectures could
add their own implementations (or it could be made
non-architecture-specific in the future).
-Scott
^ permalink raw reply
* Re: [PATCH v6] introduce macro spin_event_timeout()
From: Kumar Gala @ 2009-05-01 20:51 UTC (permalink / raw)
To: Timur Tabi; +Cc: scottwood, linuxppc-dev
In-Reply-To: <1240859144-20893-1-git-send-email-timur@freescale.com>
On Apr 27, 2009, at 2:05 PM, Timur Tabi wrote:
> The macro spin_event_timeout() takes a condition and timeout value
> (in microseconds) as parameters. It spins until either the
> condition is true
> or the timeout expires. It returns the result of the condition when
> the loop
> was terminated.
>
> This primary purpose of this macro is to poll on a hardware register
> until a
> status bit changes. The timeout ensures that the loop still
> terminates if the
> bit doesn't change as expected. This macro makes it easier for driver
> developers to perform this kind of operation properly.
>
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
>
> I'm making this a PowerPC-specific patch because I want to use
> tb_ticks_per_usec, which does not exist on all other platforms. I
> don't want
> to use jiffies because jiffies works only when interrupts are
> enabled, and
> the resolution may not be fine enough.
>
> arch/powerpc/include/asm/delay.h | 27 +++++++++++++++++++++++++++
> 1 files changed, 27 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/delay.h b/arch/powerpc/include/
> asm/delay.h
> index f9200a6..1939e0f 100644
> --- a/arch/powerpc/include/asm/delay.h
> +++ b/arch/powerpc/include/asm/delay.h
> @@ -2,6 +2,8 @@
> #define _ASM_POWERPC_DELAY_H
> #ifdef __KERNEL__
>
> +#include <asm/time.h>
> +
> /*
> * Copyright 1996, Paul Mackerras.
> *
> @@ -30,5 +32,30 @@ extern void udelay(unsigned long usecs);
> #define mdelay(n) udelay((n) * 1000)
> #endif
>
> +/**
> + * spin_event_timeout - spin until a condition gets true or a
> timeout elapses
> + * @condition: a C expression to evalate
> + * @timeout: timeout, in microseconds
> + * @delay: the number of microseconds to delay between eache
> evaluation of
> + * @condition
> + * @rc: the last value of the condition
> + *
> + * The process spins until the condition evaluates to true (non-
> zero) or the
> + * timeout elapses. Upon exit, @rc contains the value of the
> condition. This
> + * allows you to test the condition without incurring any side
> effects.
> + *
> + * This primary purpose of this macro is to poll on a hardware
> register
> + * until a status bit changes. The timeout ensures that the loop
> still
> + * terminates if the bit never changes. The delay is for devices
> that need a
> + * delay in between successive reads.
> + */
> +#define spin_event_timeout(condition, timeout, delay,
> rc) \
> +
> { \
> + unsigned long __loops = tb_ticks_per_usec *
> timeout; \
> + unsigned long __start =
> get_tbl(); \
> + while (!(rc = (condition)) && (tb_ticks_since(__start) <=
> __loops)) \
> + udelay(delay); \
> +}
> +
I wouldn't call it spin_event_timeout as its a bit too generic of a
name for something that is arch specific.
- k
^ permalink raw reply
* Re: [PATCH 5/6 v2] net/ucc_geth: Assign six threads to Rx for UEC
From: Timur Tabi @ 2009-05-01 20:17 UTC (permalink / raw)
To: Haiying Wang; +Cc: linuxppc-dev
In-Reply-To: <1241206851-27749-3-git-send-email-Haiying.Wang@freescale.com>
On Fri, May 1, 2009 at 2:40 PM, Haiying Wang <Haiying.Wang@freescale.com> wrote:
> in the case the QE has 46 SNUMs for the threads to support four UCC Ethernet at
> 1000Base-T simultaneously.
>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
FYI, this should have been cross-posted to the netdev mailing list.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [PATCH 2/6 v2] powerpc/qe: update risc allocation for QE
From: Timur Tabi @ 2009-05-01 20:15 UTC (permalink / raw)
To: Haiying Wang; +Cc: linuxppc-dev
In-Reply-To: <1241206851-27749-1-git-send-email-Haiying.Wang@freescale.com>
On Fri, May 1, 2009 at 2:40 PM, Haiying Wang <Haiying.Wang@freescale.com> wrote:
> Change the RISC allocation to macros instead of enum, add function to read the
> number of risc engines from the new property "fsl,qe-num-riscs" under qe node
> in dts. Add new property "fsl,qe-num-riscs" description in qe.txt
>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [PATCH 4/6 v2] powerpc/qe: update QE Serial Number
From: Timur Tabi @ 2009-05-01 20:14 UTC (permalink / raw)
To: Haiying Wang; +Cc: linuxppc-dev
In-Reply-To: <1241206851-27749-2-git-send-email-Haiying.Wang@freescale.com>
On Fri, May 1, 2009 at 2:40 PM, Haiying Wang <Haiying.Wang@freescale.com> wrote:
> The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will
> get the number of SNUMs from device tree by reading the new property
> "fsl,qe-num-snums", and set 28 as the default number of SNUMs so that it is
> compatible with the old QE chips' device trees which don't have this new
> property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum
> table which is 256.
> Also we update the snum_init[] array with 18 more new SNUMs which are
> confirmed to be useful on new chip.
>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: Should ppc32 use CONFIG_HIGHPTE or not?
From: Benjamin Herrenschmidt @ 2009-05-01 20:14 UTC (permalink / raw)
To: Dave Hansen; +Cc: linuxppc-dev, Paul Mackerras, Kumar Gala
In-Reply-To: <1241203023.29485.218.camel@nimitz>
On Fri, 2009-05-01 at 11:37 -0700, Dave Hansen wrote:
.../...
> So, it looks like ppc32 never actually allocates highmem pte pages, but
> it *does* go to the trouble of at least trying to kmap_atomic() them.
> Should we just give ppc32 unconditional direct-mapped ptes? Or, should
> we remove that #ifdef and let it allocate them in highmem when it can
> since we also have the code to support that?
We actually noticed that recently :-)
We implemented HIGHPTE support a long time ago, and then somebody
disabled HIGHPTE for both x86 and powerpc on the ground that it wasn't
reliable, I don't remember off hand who, I think it was in the 2.5.x
timeframe, and while it got re-enabled on x86 it never was on powerpc
(maybe because we never noticed it was disabled in the first place ;-)
Now, recently, some changes went in that could possibly be problematic
with HIGHPTE, at least I have a vague recollection of that, I think
Kumar was involved... Kumar, was this fixed ?
So depending on that, maybe we could revive the option ... or just
get rid of that HIGHPTE support and be done with it.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: add new qe properties for QE based chips
From: Timur Tabi @ 2009-05-01 20:13 UTC (permalink / raw)
To: Haiying Wang; +Cc: linuxppc-dev
In-Reply-To: <1241206851-27749-5-git-send-email-Haiying.Wang@freescale.com>
On Fri, May 1, 2009 at 2:40 PM, Haiying Wang <Haiying.Wang@freescale.com> wrote:
> Add fsl,qe-num-riscs and fsl,qe-num-snums to all the devices trees which have qe
> node.
>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* [PATCH] powerpc/85xx: add new qe properties for QE based chips
From: Haiying Wang @ 2009-05-01 19:40 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
In-Reply-To: <1241206851-27749-4-git-send-email-Haiying.Wang@freescale.com>
Add fsl,qe-num-riscs and fsl,qe-num-snums to all the devices trees which have qe
node.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
arch/powerpc/boot/dts/mpc832x_mds.dts | 2 ++
arch/powerpc/boot/dts/mpc832x_rdb.dts | 2 ++
arch/powerpc/boot/dts/mpc836x_mds.dts | 2 ++
arch/powerpc/boot/dts/mpc836x_rdk.dts | 2 ++
arch/powerpc/boot/dts/mpc8568mds.dts | 2 ++
5 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 6b319f5..436c9c6 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -249,6 +249,8 @@
reg = <0xe0100000 0x480>;
brg-frequency = <0>;
bus-frequency = <198000000>;
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
muram@10000 {
#address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 4c0c249..9a0952f 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -221,6 +221,8 @@
reg = <0xe0100000 0x480>;
brg-frequency = <0>;
bus-frequency = <198000000>;
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
muram@10000 {
#address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 1207ec8..39ff4c8 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -289,6 +289,8 @@
reg = <0xe0100000 0x480>;
brg-frequency = <0>;
bus-frequency = <396000000>;
+ fsl,qe-num-riscs = <2>;
+ fsl,qe-num-snums = <28>;
muram@10000 {
#address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index 37b7895..6315d6f 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -198,6 +198,8 @@
clock-frequency = <0>;
bus-frequency = <0>;
brg-frequency = <0>;
+ fsl,qe-num-riscs = <2>;
+ fsl,qe-num-snums = <28>;
muram@10000 {
#address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index d2fb639..fcab168 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -362,6 +362,8 @@
reg = <0xe0080000 0x480>;
brg-frequency = <0>;
bus-frequency = <396000000>;
+ fsl,qe-num-riscs = <2>;
+ fsl,qe-num-snums = <28>;
muram@10000 {
#address-cells = <1>;
--
1.6.0.2
^ permalink raw reply related
* [PATCH 6/6 v2] powerpc/85xx: Add MPC8569MDS board support
From: Haiying Wang @ 2009-05-01 19:40 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
In-Reply-To: <1241206851-27749-3-git-send-email-Haiying.Wang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
v2 change: rename "num-riscs" to "fsl,qe-num-riscs", and "num-snums" to
"fsl,qe-num-snums".
arch/powerpc/boot/dts/mpc8569mds.dts | 514 +++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 23 ++
2 files changed, 537 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc8569mds.dts
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
new file mode 100644
index 0000000..3ddd8c3
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -0,0 +1,514 @@
+/*
+ * MPC8569E MDS Device Tree Source
+ *
+ * Copyright (C) 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "MPC8569EMDS";
+ compatible = "fsl,MPC8569EMDS";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8569@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xe0005000 0 0x1000>;
+ interrupt = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ ranges = <0x0 0x0 0xfe000000 0x02000000
+ 0x1 0x0 0xf8000000 0x00008000
+ 0x2 0x0 0xf0000000 0x04000000
+ 0x4 0x0 0xf8008000 0x00008000
+ 0x5 0x0 0xf8010000 0x00008000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ bcsr@1,0 {
+ compatible = "fsl,mpc8569mds-bcsr";
+ reg = <1 0 0x8000>;
+ };
+
+ pib@4,0 {
+ compatible = "fsl,mpc8569mds-pib";
+ reg = <4 0 0x8000>;
+ };
+
+ pib@5,0 {
+ compatible = "fsl,mpc8569mds-pib";
+ reg = <5 0 0x8000>;
+ };
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8569-immr", "simple-bus";
+ ranges = <0x0 0xe0000000 0x100000>;
+ reg = <0xe0000000 0x1000>;
+ bus-frequency = <0>;
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <10>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,mpc8569-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8569-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ rtc@68 {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,mpc8569-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8569-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8569-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8569-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8569-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ global-utilities@e0000 {
+ compatible = "fsl,mpc8569-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ par_io@e0100 {
+ reg = <0xe0100 0x100>;
+ device_type = "par_io";
+ num-ports = <7>;
+
+ pio1: ucc_pin@01 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
+ 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
+ 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
+ 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
+ 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
+ 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
+ 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
+ 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
+ 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
+ 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
+ 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
+ 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
+ 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
+ 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
+ };
+
+ pio2: ucc_pin@02 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
+ 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
+ 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
+ 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
+ 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
+ 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
+ 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
+ 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
+ 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
+ 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
+ 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
+ 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
+ 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
+ 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
+ };
+
+ pio3: ucc_pin@03 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
+ 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
+ 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
+ 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
+ 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
+ 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
+ 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
+ 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
+ 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
+ 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
+ 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
+ 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
+ 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
+ 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
+ };
+
+ pio4: ucc_pin@04 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
+ 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
+ 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
+ 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
+ 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
+ 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
+ 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
+ 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
+ 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
+ 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
+ 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
+ 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
+ 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
+ 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
+ };
+ };
+ };
+
+ qe@e0080000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe";
+ ranges = <0x0 0xe0080000 0x40000>;
+ reg = <0xe0080000 0x480>;
+ brg-frequency = <0>;
+ bus-frequency = <0>;
+ fsl,qe-num-riscs = <4>;
+ fsl,qe-num-snums = <46>;
+
+ qeic: interrupt-controller@80 {
+ interrupt-controller;
+ compatible = "fsl,qe-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ interrupts = <46 2 46 2>; //high:30 low:30
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@4c0 {
+ cell-index = <0>;
+ compatible = "fsl,spi";
+ reg = <0x4c0 0x40>;
+ interrupts = <2>;
+ interrupt-parent = <&qeic>;
+ mode = "cpu";
+ };
+
+ spi@500 {
+ cell-index = <1>;
+ compatible = "fsl,spi";
+ reg = <0x500 0x40>;
+ interrupts = <1>;
+ interrupt-parent = <&qeic>;
+ mode = "cpu";
+ };
+
+ enet0: ucc@2000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk12";
+ pio-handle = <&pio1>;
+ phy-handle = <&qe_phy0>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ mdio@2120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2120 0x18>;
+ compatible = "fsl,ucc-mdio";
+
+ qe_phy0: ethernet-phy@07 {
+ interrupt-parent = <&mpic>;
+ interrupts = <1 1>;
+ reg = <0x7>;
+ device_type = "ethernet-phy";
+ };
+ qe_phy1: ethernet-phy@01 {
+ interrupt-parent = <&mpic>;
+ interrupts = <2 1>;
+ reg = <0x1>;
+ device_type = "ethernet-phy";
+ };
+ qe_phy2: ethernet-phy@02 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x2>;
+ device_type = "ethernet-phy";
+ };
+ qe_phy3: ethernet-phy@03 {
+ interrupt-parent = <&mpic>;
+ interrupts = <4 1>;
+ reg = <0x3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet2: ucc@2200 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk12";
+ pio-handle = <&pio3>;
+ phy-handle = <&qe_phy2>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet1: ucc@3000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <2>;
+ reg = <0x3000 0x200>;
+ interrupts = <33>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk17";
+ pio-handle = <&pio2>;
+ phy-handle = <&qe_phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet3: ucc@3200 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <4>;
+ reg = <0x3200 0x200>;
+ interrupts = <35>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk17";
+ pio-handle = <&pio4>;
+ phy-handle = <&qe_phy3>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x20000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x20000>;
+ };
+ };
+
+ };
+
+ /* PCI Express */
+ pci1: pcie@e000a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xe000a000 0x1000>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 (PEX) */
+ 00000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 00000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 00000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
+ clock-frequency = <33333333>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x800000>;
+ };
+ };
+};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d34d29a..b2c0a43 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -259,6 +259,7 @@ static int __init board_fixups(void)
return 0;
}
machine_arch_initcall(mpc8568_mds, board_fixups);
+machine_arch_initcall(mpc8569_mds, board_fixups);
static struct of_device_id mpc85xx_ids[] = {
{ .type = "soc", },
@@ -278,6 +279,7 @@ static int __init mpc85xx_publish_devices(void)
return 0;
}
machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
+machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
static void __init mpc85xx_mds_pic_init(void)
{
@@ -335,3 +337,24 @@ define_machine(mpc8568_mds) {
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
};
+
+static int __init mpc8569_mds_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
+}
+
+define_machine(mpc8569_mds) {
+ .name = "MPC8569 MDS",
+ .probe = mpc8569_mds_probe,
+ .setup_arch = mpc85xx_mds_setup_arch,
+ .init_IRQ = mpc85xx_mds_pic_init,
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+};
--
1.6.0.2
^ permalink raw reply related
* [PATCH 4/6 v2] powerpc/qe: update QE Serial Number
From: Haiying Wang @ 2009-05-01 19:40 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
In-Reply-To: <1241206851-27749-1-git-send-email-Haiying.Wang@freescale.com>
The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will
get the number of SNUMs from device tree by reading the new property
"fsl,qe-num-snums", and set 28 as the default number of SNUMs so that it is
compatible with the old QE chips' device trees which don't have this new
property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum
table which is 256.
Also we update the snum_init[] array with 18 more new SNUMs which are
confirmed to be useful on new chip.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
v2 change: rename the new property as "fsl,qe-num-snums" and move it to Required
section in qe.txt
.../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 2 +
arch/powerpc/include/asm/qe.h | 3 +-
arch/powerpc/sysdev/qe_lib/qe.c | 47 ++++++++++++++++++--
3 files changed, 47 insertions(+), 5 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
index 39b5d1f..6e37be1 100644
--- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -18,6 +18,8 @@ Required properties:
- reg : offset and length of the device registers.
- bus-frequency : the clock frequency for QUICC Engine.
- fsl,qe-num-riscs: define how many RISC engines the QE has.
+- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the
+ threads.
Recommended properties
- brg-frequency : the internal clock source frequency for baud-rate
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 60314ef..e0faf33 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -22,7 +22,7 @@
#include <asm/cpm.h>
#include <asm/immap_qe.h>
-#define QE_NUM_OF_SNUM 28
+#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
#define QE_NUM_OF_BRGS 16
#define QE_NUM_OF_PORTS 1024
@@ -153,6 +153,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
unsigned int qe_get_num_of_risc(void);
+unsigned int qe_get_num_of_snums(void);
/* we actually use cpm_muram implementation, define this for convenience */
#define qe_muram_init cpm_muram_init
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 2533677..b28b0e5 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -61,6 +61,7 @@ struct qe_immap __iomem *qe_immr;
EXPORT_SYMBOL(qe_immr);
static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
+static unsigned int qe_num_of_snum;
static phys_addr_t qebase = -1;
@@ -264,10 +265,14 @@ static void qe_snums_init(void)
0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
- 0xD8, 0xD9, 0xE8, 0xE9,
+ 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
+ 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
+ 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
};
- for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+ qe_num_of_snum = qe_get_num_of_snums();
+
+ for (i = 0; i < qe_num_of_snum; i++) {
snums[i].num = snum_init[i];
snums[i].state = QE_SNUM_STATE_FREE;
}
@@ -280,7 +285,7 @@ int qe_get_snum(void)
int i;
spin_lock_irqsave(&qe_lock, flags);
- for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+ for (i = 0; i < qe_num_of_snum; i++) {
if (snums[i].state == QE_SNUM_STATE_FREE) {
snums[i].state = QE_SNUM_STATE_USED;
snum = snums[i].num;
@@ -297,7 +302,7 @@ void qe_put_snum(u8 snum)
{
int i;
- for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+ for (i = 0; i < qe_num_of_snum; i++) {
if (snums[i].num == snum) {
snums[i].state = QE_SNUM_STATE_FREE;
break;
@@ -603,3 +608,37 @@ unsigned int qe_get_num_of_risc(void)
}
EXPORT_SYMBOL(qe_get_num_of_risc);
+unsigned int qe_get_num_of_snums(void)
+{
+ struct device_node *qe;
+ int size;
+ unsigned int num_of_snums;
+ const u32 *prop;
+
+ num_of_snums = 28; /* The default number of snum for threads is 28 */
+ qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
+ if (!qe) {
+ /* Older devices trees did not have an "fsl,qe"
+ * compatible property, so we need to look for
+ * the QE node by name.
+ */
+ qe = of_find_node_by_type(NULL, "qe");
+ if (!qe)
+ return num_of_snums;
+ }
+
+ prop = of_get_property(qe, "fsl,qe-num-snums", &size);
+ if (prop && size == sizeof(*prop)) {
+ num_of_snums = *prop;
+ if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
+ /* No QE ever has fewer than 28 SNUMs */
+ pr_err("QE: number of snum is invalid\n");
+ return -EINVAL;
+ }
+ }
+
+ of_node_put(qe);
+
+ return num_of_snums;
+}
+EXPORT_SYMBOL(qe_get_num_of_snums);
--
1.6.0.2
^ permalink raw reply related
* [PATCH 5/6 v2] net/ucc_geth: Assign six threads to Rx for UEC
From: Haiying Wang @ 2009-05-01 19:40 UTC (permalink / raw)
To: linuxppc-dev, galak; +Cc: Haiying Wang
In-Reply-To: <1241206851-27749-2-git-send-email-Haiying.Wang@freescale.com>
in the case the QE has 46 SNUMs for the threads to support four UCC Ethernet at
1000Base-T simultaneously.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
v2 change: Add comments for the Rx threads change.
drivers/net/ucc_geth.c | 10 +++++++++-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 44f8392..1cb2710 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -3702,7 +3702,15 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma
ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
- ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
+
+ /* If QE's snum number is 46 which means we need to support
+ * 4 UECs at 1000Base-T simultaneously, we need to allocate
+ * more Threads to Rx.
+ */
+ if (qe_get_num_of_snums() == 46)
+ ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
+ else
+ ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
}
if (netif_msg_probe(&debug))
--
1.6.0.2
^ permalink raw reply related
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