From: Kan Liang <kan.liang@intel.com>
To: a.p.zijlstra@chello.nl, eranian@google.com
Cc: linux-kernel@vger.kernel.org, mingo@redhat.com, paulus@samba.org,
acme@kernel.org, jolsa@redhat.com, ak@linux.intel.com,
Kan Liang <kan.liang@intel.com>
Subject: [PATCH V8 10/14] perf, core: simplify need branch stack check
Date: Thu, 6 Nov 2014 09:54:27 -0500 [thread overview]
Message-ID: <1415285671-16894-11-git-send-email-kan.liang@intel.com> (raw)
In-Reply-To: <1415285671-16894-1-git-send-email-kan.liang@intel.com>
From: Yan, Zheng <zheng.z.yan@intel.com>
Using event->attr.branch_sample_type to replace
intel_pmu_needs_lbr_smpl() for avoiding duplicating code
that implicitly enables the LBR.
Currently, branch stack can be enabled by user explicitly requested
branch sampling or implicit branch sampling to correct PEBS skid.
For user explicitly requested branch sampling, the branch_sample_type is
explicitly set by user. For PEBS case, the branch_sample_type is also
implicitly set to PERF_SAMPLE_BRANCH_ANY in x86_pmu_hw_config.
Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: Kan Liang <kan.liang@intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 20 +++-----------------
include/linux/perf_event.h | 5 +++++
kernel/events/core.c | 3 +++
3 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index a0c0739..5f449fb 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1029,20 +1029,6 @@ static __initconst const u64 slm_hw_cache_event_ids
},
};
-static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
-{
- /* user explicitly requested branch sampling */
- if (has_branch_stack(event))
- return true;
-
- /* implicit branch sampling to correct PEBS skid */
- if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
- x86_pmu.intel_cap.pebs_format < 2)
- return true;
-
- return false;
-}
-
static void intel_pmu_disable_all(void)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -1207,7 +1193,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
* must disable before any actual event
* because any event may be combined with LBR
*/
- if (intel_pmu_needs_lbr_smpl(event))
+ if (needs_branch_stack(event))
intel_pmu_lbr_disable(event);
if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
@@ -1268,7 +1254,7 @@ static void intel_pmu_enable_event(struct perf_event *event)
* must enabled before any actual event
* because any event may be combined with LBR
*/
- if (intel_pmu_needs_lbr_smpl(event))
+ if (needs_branch_stack(event))
intel_pmu_lbr_enable(event);
if (event->attr.exclude_host)
@@ -1747,7 +1733,7 @@ static int intel_pmu_hw_config(struct perf_event *event)
if (event->attr.precise_ip && x86_pmu.pebs_aliases)
x86_pmu.pebs_aliases(event);
- if (intel_pmu_needs_lbr_smpl(event)) {
+ if (needs_branch_stack(event)) {
ret = intel_pmu_setup_lbr_filter(event);
if (ret)
return ret;
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 84ec3e6..0d67460 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -796,6 +796,11 @@ static inline bool has_branch_stack(struct perf_event *event)
return event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK;
}
+static inline bool needs_branch_stack(struct perf_event *event)
+{
+ return event->attr.branch_sample_type != 0;
+}
+
extern int perf_output_begin(struct perf_output_handle *handle,
struct perf_event *event, unsigned int size);
extern void perf_output_end(struct perf_output_handle *handle);
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 4360c95..3f3e43d 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -7015,6 +7015,9 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu,
if (attr->inherit && (attr->read_format & PERF_FORMAT_GROUP))
goto err_ns;
+ if (!has_branch_stack(event))
+ event->attr.branch_sample_type = 0;
+
pmu = perf_init_event(event);
if (!pmu)
goto err_ns;
--
1.8.3.2
next prev parent reply other threads:[~2014-11-06 15:11 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-06 14:54 [PATCH V8 00/14] perf, x86: Haswell LBR call stack support (kernel) Kan Liang
2014-11-06 14:54 ` [PATCH V8 01/14] perf, x86: Reduce lbr_sel_map size Kan Liang
2014-11-06 14:54 ` [PATCH V8 02/14] perf, core: introduce pmu context switch callback Kan Liang
2014-11-06 14:54 ` [PATCH V8 03/14] perf, x86: use context switch callback to flush LBR stack Kan Liang
2015-01-14 13:29 ` Peter Zijlstra
2015-01-14 14:16 ` Liang, Kan
2014-11-06 14:54 ` [PATCH V8 04/14] perf, x86: Basic Haswell LBR call stack support Kan Liang
2014-11-06 14:54 ` [PATCH V8 05/14] perf, core: pmu specific data for perf task context Kan Liang
2014-11-06 14:54 ` [PATCH V8 06/14] perf, core: always switch pmu specific data during context switch Kan Liang
2014-11-06 14:54 ` [PATCH V8 07/14] perf, x86: allocate space for storing LBR stack Kan Liang
2014-11-06 14:54 ` [PATCH V8 08/14] perf, x86: track number of events that use LBR callstack Kan Liang
2014-11-06 14:54 ` [PATCH V8 09/14] perf, x86: Save/resotre LBR stack during context switch Kan Liang
2014-11-06 14:54 ` Kan Liang [this message]
2014-11-06 14:54 ` [PATCH V8 11/14] perf, x86: re-organize code that implicitly enables LBR/PEBS Kan Liang
2014-11-06 14:54 ` [PATCH V8 12/14] perf, x86: disable FREEZE_LBRS_ON_PMI when LBR operates in callstack mode Kan Liang
2014-11-06 14:54 ` [PATCH V8 13/14] perf, x86: Discard zero length call entries in LBR call stack Kan Liang
2014-11-06 14:54 ` [PATCH V8 14/14] perf, x86: expose LBR callstack to user space tool Kan Liang
2014-11-10 10:13 ` [PATCH V8 00/14] perf, x86: Haswell LBR call stack support (kernel) Peter Zijlstra
2014-11-10 13:54 ` Liang, Kan
2014-11-10 14:03 ` Peter Zijlstra
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