* [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1
@ 2025-01-10 11:55 shiju.jose
2025-01-10 11:55 ` [PATCH v5 1/6] cxl/events: Update Common Event Record " shiju.jose
` (6 more replies)
0 siblings, 7 replies; 19+ messages in thread
From: shiju.jose @ 2025-01-10 11:55 UTC (permalink / raw)
To: dave.jiang, dan.j.williams, jonathan.cameron, alison.schofield,
nifan.cxl, vishal.l.verma, ira.weiny, dave, linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
Add updates in the CXL events records and CXL trace events implementations
for the changes in CXL spec rev 3.1.
Shiju Jose (6):
cxl/events: Update Common Event Record to CXL spec rev 3.1
cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
cxl/events: Update General Media Event Record to CXL spec rev 3.1
cxl/events: Update DRAM Event Record to CXL spec rev 3.1
cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
cxl/test: Update test code for event records to CXL spec rev 3.1
Changes:
V4 -> V5
1. Reverted changes made in v4 for overcoming parsing error when
libtraceevent in userspace parses the CXL trace events, for rasdaemon.
This was due to trace event's format file is larger than PAGE_SIZE, not
supported reading complete format file in one go in the kernel and thus
fixed in the rasdaemon.
2. Rebased to v6.13-rc5.
3. Tested with rasdaemon and ras-mc-ctl tools updated for CXL spec rev 3.1
event record changes.
V3 -> V4
1. Changes for the parsing error parsing error when libtraceevent in
userspace parses the CXL trace events, for rasdaemon.
It was found that long decoded strings of field values in the TP_printk()
caused the issue, looks like due to buffer overflow/corruption.
Increasing known buffer sizes in userspace and kernel did not help.
As a solution, decoding of some fields in the TP_printk() are removed
to accommodate the new fields.
Decoding of these fields is added in the userspace tool rasdaemon.
V2 -> V3
1. Changes for the feedbacks from Jonathan.
- Added printing component Id format bit in show_valid_flags()
- Modified parsing component ID in patch [2] and added logging
of raw comp-id, comp_id_pldm_flags, PLDM entity id and
PLDM resource id in patches 3 to 4.
V1 -> V2
1. Changes for the feedbacks from Jonathan.
- Separate patch for Component Identifier formatting.
- Moved printing of event sub type after event type.
- For memory module event, rename sub_type to event_sub_type.
2. Changes for the feedbacks from Alison.
- Updated patch's subject
- Updated CXL test code for CXL spec rev 3.1 event records.
3. Changed logic for Component Identifier formatting and other improvements.
drivers/cxl/core/trace.h | 258 +++++++++++++++++++++++++++++------
include/cxl/event.h | 28 ++--
tools/testing/cxl/test/mem.c | 23 +++-
3 files changed, 256 insertions(+), 53 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v5 1/6] cxl/events: Update Common Event Record to CXL spec rev 3.1
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
@ 2025-01-10 11:55 ` shiju.jose
2025-01-10 17:35 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 2/6] cxl/events: Add Component Identifier formatting for " shiju.jose
` (5 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: shiju.jose @ 2025-01-10 11:55 UTC (permalink / raw)
To: dave.jiang, dan.j.williams, jonathan.cameron, alison.schofield,
nifan.cxl, vishal.l.verma, ira.weiny, dave, linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec 3.1 section 8.2.9.2.1 Table 8-42, Common Event Record format has
updated with Maintenance Operation Subclass information.
Add updates for the above spec change in the CXL events record and CXL
common trace event implementations.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
drivers/cxl/core/trace.h | 13 +++++++++----
include/cxl/event.h | 3 ++-
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index 8389a94adb1a..7305974e2301 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -166,11 +166,13 @@ TRACE_EVENT(cxl_overflow,
#define CXL_EVENT_RECORD_FLAG_MAINT_NEEDED BIT(3)
#define CXL_EVENT_RECORD_FLAG_PERF_DEGRADED BIT(4)
#define CXL_EVENT_RECORD_FLAG_HW_REPLACE BIT(5)
+#define CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID BIT(6)
#define show_hdr_flags(flags) __print_flags(flags, " | ", \
{ CXL_EVENT_RECORD_FLAG_PERMANENT, "PERMANENT_CONDITION" }, \
{ CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, "MAINTENANCE_NEEDED" }, \
{ CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, "PERFORMANCE_DEGRADED" }, \
- { CXL_EVENT_RECORD_FLAG_HW_REPLACE, "HARDWARE_REPLACEMENT_NEEDED" } \
+ { CXL_EVENT_RECORD_FLAG_HW_REPLACE, "HARDWARE_REPLACEMENT_NEEDED" }, \
+ { CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID, "MAINT_OP_SUB_CLASS_VALID" } \
)
/*
@@ -197,7 +199,8 @@ TRACE_EVENT(cxl_overflow,
__field(u16, hdr_related_handle) \
__field(u64, hdr_timestamp) \
__field(u8, hdr_length) \
- __field(u8, hdr_maint_op_class)
+ __field(u8, hdr_maint_op_class) \
+ __field(u8, hdr_maint_op_sub_class)
#define CXL_EVT_TP_fast_assign(cxlmd, l, hdr) \
__assign_str(memdev); \
@@ -209,17 +212,19 @@ TRACE_EVENT(cxl_overflow,
__entry->hdr_handle = le16_to_cpu((hdr).handle); \
__entry->hdr_related_handle = le16_to_cpu((hdr).related_handle); \
__entry->hdr_timestamp = le64_to_cpu((hdr).timestamp); \
- __entry->hdr_maint_op_class = (hdr).maint_op_class
+ __entry->hdr_maint_op_class = (hdr).maint_op_class; \
+ __entry->hdr_maint_op_sub_class = (hdr).maint_op_sub_class
#define CXL_EVT_TP_printk(fmt, ...) \
TP_printk("memdev=%s host=%s serial=%lld log=%s : time=%llu uuid=%pUb " \
"len=%d flags='%s' handle=%x related_handle=%x " \
- "maint_op_class=%u : " fmt, \
+ "maint_op_class=%u maint_op_sub_class=%u : " fmt, \
__get_str(memdev), __get_str(host), __entry->serial, \
cxl_event_log_type_str(__entry->log), \
__entry->hdr_timestamp, &__entry->hdr_uuid, __entry->hdr_length,\
show_hdr_flags(__entry->hdr_flags), __entry->hdr_handle, \
__entry->hdr_related_handle, __entry->hdr_maint_op_class, \
+ __entry->hdr_maint_op_sub_class, \
##__VA_ARGS__)
TRACE_EVENT(cxl_generic_event,
diff --git a/include/cxl/event.h b/include/cxl/event.h
index 0bea1afbd747..e1d485ad376b 100644
--- a/include/cxl/event.h
+++ b/include/cxl/event.h
@@ -18,7 +18,8 @@ struct cxl_event_record_hdr {
__le16 related_handle;
__le64 timestamp;
u8 maint_op_class;
- u8 reserved[15];
+ u8 maint_op_sub_class;
+ u8 reserved[14];
} __packed;
struct cxl_event_media_hdr {
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v5 2/6] cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
2025-01-10 11:55 ` [PATCH v5 1/6] cxl/events: Update Common Event Record " shiju.jose
@ 2025-01-10 11:55 ` shiju.jose
2025-01-10 17:43 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 3/6] cxl/events: Update General Media Event Record to " shiju.jose
` (4 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: shiju.jose @ 2025-01-10 11:55 UTC (permalink / raw)
To: dave.jiang, dan.j.williams, jonathan.cameron, alison.schofield,
nifan.cxl, vishal.l.verma, ira.weiny, dave, linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
Add Component Identifier formatting for CXL spec rev 3.1, Section
8.2.9.2.1, Table 8-44.
Examples for Component Identifier format in trace log,
validity_flags='CHANNEL|RANK|DEVICE|COMPONENT|COMPONENT PLDM FORMAT' \
comp_id=03 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
comp_id_pldm_valid_flags='PLDM Entity ID | Resource ID' \
pldm_entity_id=74 c5 08 9a 1a 0b pldm_resource_id=fc d2 7e 2f \
validity_flags='COMPONENT|COMPONENT PLDM FORMAT' \
comp_id=02 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
comp_id_pldm_valid_flags='Resource ID' \
pldm_entity_id=0x00 pldm_resource_id=fc d2 7e 2f
If the validity flags for component ID/component ID format or PLDM ID or
resource ID are not set, then pldm_entity_id=0x00 or pldm_resource_id=0x00
would be printed.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
drivers/cxl/core/trace.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index 7305974e2301..b508873ce426 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -268,6 +268,28 @@ TRACE_EVENT(cxl_generic_event,
{ CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \
)
+/*
+ * Component ID Format
+ * CXL 3.1 section 8.2.9.2.1; Table 8-44
+ */
+#define CXL_PLDM_COMPONENT_ID_ENTITY_VALID BIT(0)
+#define CXL_PLDM_COMPONENT_ID_RES_VALID BIT(1)
+
+#define show_comp_id_pldm_flags(flags) __print_flags(flags, " | ", \
+ { CXL_PLDM_COMPONENT_ID_ENTITY_VALID, "PLDM Entity ID" }, \
+ { CXL_PLDM_COMPONENT_ID_RES_VALID, "Resource ID" } \
+)
+
+#define show_pldm_entity_id(flags, valid_comp_id, valid_id_format, comp_id) \
+ (flags & valid_comp_id && flags & valid_id_format) ? \
+ (comp_id[0] & CXL_PLDM_COMPONENT_ID_ENTITY_VALID) ? \
+ __print_hex(&comp_id[1], 6) : "0x00" : "0x00"
+
+#define show_pldm_resource_id(flags, valid_comp_id, valid_id_format, comp_id) \
+ (flags & valid_comp_id && flags & valid_id_format) ? \
+ (comp_id[0] & CXL_PLDM_COMPONENT_ID_RES_VALID) ? \
+ __print_hex(&comp_id[7], 4) : "0x00" : "0x00"
+
/*
* General Media Event Record - GMER
* CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v5 3/6] cxl/events: Update General Media Event Record to CXL spec rev 3.1
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
2025-01-10 11:55 ` [PATCH v5 1/6] cxl/events: Update Common Event Record " shiju.jose
2025-01-10 11:55 ` [PATCH v5 2/6] cxl/events: Add Component Identifier formatting for " shiju.jose
@ 2025-01-10 11:55 ` shiju.jose
2025-01-10 17:54 ` Ira Weiny
2025-01-10 18:30 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 4/6] cxl/events: Update DRAM " shiju.jose
` (3 subsequent siblings)
6 siblings, 2 replies; 19+ messages in thread
From: shiju.jose @ 2025-01-10 11:55 UTC (permalink / raw)
To: dave.jiang, dan.j.williams, jonathan.cameron, alison.schofield,
nifan.cxl, vishal.l.verma, ira.weiny, dave, linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev 3.1 section 8.2.9.2.1.1 Table 8-45, General Media Event
Record has updated with following new fields and new types for Memory
Event Type and Transaction Type fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
The format of component identifier has changed (CXL spec 3.1 section
8.2.9.2.1 Table 8-44).
Update the general media event record and general media trace event for
the above spec changes. The new fields are inserted in logical places.
Example trace log of cxl_general_media trace event,
cxl_general_media: memdev=mem0 host=0000:0f:00.0 serial=3 log=Fatal : \
time=156831237413 uuid=fbcd0a77-c260-417f-85a9-088b1621eba6 len=128 \
flags='0x1' handle=1 related_handle=0 maint_op_class=2 \
maint_op_sub_class=4 : dpa=30d40 dpa_flags='' \
descriptor='UNCORRECTABLE_EVENT|THRESHOLD_EVENT|POISON_LIST_OVERFLOW' \
type='TE State Violation' sub_type='Media Link Command Training Error' \
transaction_type='Host Inject Poison' channel=3 rank=33 device=5 \
validity_flags='CHANNEL|RANK|DEVICE|COMPONENT|COMPONENT PLDM FORMAT' \
comp_id=03 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
comp_id_pldm_valid_flags='PLDM Entity ID | Resource ID' \
pldm_entity_id=74 c5 08 9a 1a 0b pldm_resource_id=fc d2 7e 2f \
hpa=ffffffffffffffff region= \
region_uuid=00000000-0000-0000-0000-000000000000 \
cme_threshold_ev_flags='Corrected Memory Errors in Multiple Media \
Components|Exceeded Programmable Threshold' cme_count=120
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
drivers/cxl/core/trace.h | 90 ++++++++++++++++++++++++++++++++++------
include/cxl/event.h | 7 +++-
2 files changed, 83 insertions(+), 14 deletions(-)
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index b508873ce426..241c10596f4d 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -292,7 +292,7 @@ TRACE_EVENT(cxl_generic_event,
/*
* General Media Event Record - GMER
- * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
+ * CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45
*/
#define CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT BIT(0)
#define CXL_GMER_EVT_DESC_THRESHOLD_EVENT BIT(1)
@@ -306,10 +306,18 @@ TRACE_EVENT(cxl_generic_event,
#define CXL_GMER_MEM_EVT_TYPE_ECC_ERROR 0x00
#define CXL_GMER_MEM_EVT_TYPE_INV_ADDR 0x01
#define CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x02
-#define show_gmer_mem_event_type(type) __print_symbolic(type, \
- { CXL_GMER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \
- { CXL_GMER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \
- { CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" } \
+#define CXL_GMER_MEM_EVT_TYPE_TE_STATE_VIOLATION 0x03
+#define CXL_GMER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x04
+#define CXL_GMER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE 0x05
+#define CXL_GMER_MEM_EVT_TYPE_CKID_VIOLATION 0x06
+#define show_gmer_mem_event_type(type) __print_symbolic(type, \
+ { CXL_GMER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \
+ { CXL_GMER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \
+ { CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" }, \
+ { CXL_GMER_MEM_EVT_TYPE_TE_STATE_VIOLATION, "TE State Violation" }, \
+ { CXL_GMER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \
+ { CXL_GMER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE, "Adv Prog CME Counter Expiration" }, \
+ { CXL_GMER_MEM_EVT_TYPE_CKID_VIOLATION, "CKID Violation" } \
)
#define CXL_GMER_TRANS_UNKNOWN 0x00
@@ -319,6 +327,8 @@ TRACE_EVENT(cxl_generic_event,
#define CXL_GMER_TRANS_HOST_INJECT_POISON 0x04
#define CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB 0x05
#define CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT 0x06
+#define CXL_GMER_TRANS_INTERNAL_MEDIA_ECS 0x07
+#define CXL_GMER_TRANS_MEDIA_INITIALIZATION 0x08
#define show_trans_type(type) __print_symbolic(type, \
{ CXL_GMER_TRANS_UNKNOWN, "Unknown" }, \
{ CXL_GMER_TRANS_HOST_READ, "Host Read" }, \
@@ -326,18 +336,57 @@ TRACE_EVENT(cxl_generic_event,
{ CXL_GMER_TRANS_HOST_SCAN_MEDIA, "Host Scan Media" }, \
{ CXL_GMER_TRANS_HOST_INJECT_POISON, "Host Inject Poison" }, \
{ CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, "Internal Media Scrub" }, \
- { CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT, "Internal Media Management" } \
+ { CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT, "Internal Media Management" }, \
+ { CXL_GMER_TRANS_INTERNAL_MEDIA_ECS, "Internal Media Error Check Scrub" }, \
+ { CXL_GMER_TRANS_MEDIA_INITIALIZATION, "Media Initialization" } \
)
#define CXL_GMER_VALID_CHANNEL BIT(0)
#define CXL_GMER_VALID_RANK BIT(1)
#define CXL_GMER_VALID_DEVICE BIT(2)
#define CXL_GMER_VALID_COMPONENT BIT(3)
+#define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4)
#define show_valid_flags(flags) __print_flags(flags, "|", \
{ CXL_GMER_VALID_CHANNEL, "CHANNEL" }, \
{ CXL_GMER_VALID_RANK, "RANK" }, \
{ CXL_GMER_VALID_DEVICE, "DEVICE" }, \
- { CXL_GMER_VALID_COMPONENT, "COMPONENT" } \
+ { CXL_GMER_VALID_COMPONENT, "COMPONENT" }, \
+ { CXL_GMER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" } \
+)
+
+#define CXL_GMER_CME_EV_FLAG_CME_MULTIPLE_MEDIA BIT(0)
+#define CXL_GMER_CME_EV_FLAG_THRESHOLD_EXCEEDED BIT(1)
+#define show_cme_threshold_ev_flags(flags) __print_flags(flags, "|", \
+ { \
+ CXL_GMER_CME_EV_FLAG_CME_MULTIPLE_MEDIA, \
+ "Corrected Memory Errors in Multiple Media Components" \
+ }, { \
+ CXL_GMER_CME_EV_FLAG_THRESHOLD_EXCEEDED, \
+ "Exceeded Programmable Threshold" \
+ } \
+)
+
+#define CXL_GMER_MEM_EVT_SUB_TYPE_NOT_REPORTED 0x00
+#define CXL_GMER_MEM_EVT_SUB_TYPE_INTERNAL_DATAPATH_ERROR 0x01
+#define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_COMMAND_TRAINING_ERROR 0x02
+#define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CONTROL_TRAINING_ERROR 0x03
+#define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_DATA_TRAINING_ERROR 0x04
+#define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CRC_ERROR 0x05
+#define show_mem_event_sub_type(sub_type) __print_symbolic(sub_type, \
+ { CXL_GMER_MEM_EVT_SUB_TYPE_NOT_REPORTED, "Not Reported" }, \
+ { CXL_GMER_MEM_EVT_SUB_TYPE_INTERNAL_DATAPATH_ERROR, "Internal Datapath Error" }, \
+ { \
+ CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_COMMAND_TRAINING_ERROR, \
+ "Media Link Command Training Error" \
+ }, { \
+ CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CONTROL_TRAINING_ERROR, \
+ "Media Link Control Training Error" \
+ }, { \
+ CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_DATA_TRAINING_ERROR, \
+ "Media Link Data Training Error" \
+ }, { \
+ CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CRC_ERROR, "Media Link CRC Error" \
+ } \
)
TRACE_EVENT(cxl_general_media,
@@ -353,6 +402,7 @@ TRACE_EVENT(cxl_general_media,
__field(u64, dpa)
__field(u8, descriptor)
__field(u8, type)
+ __field(u8, sub_type)
__field(u8, transaction_type)
__field(u8, channel)
__field(u32, device)
@@ -364,6 +414,8 @@ TRACE_EVENT(cxl_general_media,
__field(u8, rank)
__field(u8, dpa_flags)
__string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
+ __field(u8, cme_threshold_ev_flags)
+ __field(u32, cme_count)
),
TP_fast_assign(
@@ -377,6 +429,7 @@ TRACE_EVENT(cxl_general_media,
__entry->dpa &= CXL_DPA_MASK;
__entry->descriptor = rec->media_hdr.descriptor;
__entry->type = rec->media_hdr.type;
+ __entry->sub_type = rec->sub_type;
__entry->transaction_type = rec->media_hdr.transaction_type;
__entry->channel = rec->media_hdr.channel;
__entry->rank = rec->media_hdr.rank;
@@ -392,20 +445,33 @@ TRACE_EVENT(cxl_general_media,
__assign_str(region_name);
uuid_copy(&__entry->region_uuid, &uuid_null);
}
+ __entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags;
+ __entry->cme_count = get_unaligned_le24(rec->cme_count);
),
CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \
- "descriptor='%s' type='%s' transaction_type='%s' channel=%u rank=%u " \
- "device=%x comp_id=%s validity_flags='%s' " \
- "hpa=%llx region=%s region_uuid=%pUb",
+ "descriptor='%s' type='%s' sub_type='%s' " \
+ "transaction_type='%s' channel=%u rank=%u " \
+ "device=%x validity_flags='%s' " \
+ "comp_id=%s comp_id_pldm_valid_flags='%s' " \
+ "pldm_entity_id=%s pldm_resource_id=%s " \
+ "hpa=%llx region=%s region_uuid=%pUb " \
+ "cme_threshold_ev_flags='%s' cme_count=%u",
__entry->dpa, show_dpa_flags(__entry->dpa_flags),
show_event_desc_flags(__entry->descriptor),
show_gmer_mem_event_type(__entry->type),
+ show_mem_event_sub_type(__entry->sub_type),
show_trans_type(__entry->transaction_type),
__entry->channel, __entry->rank, __entry->device,
- __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE),
show_valid_flags(__entry->validity_flags),
- __entry->hpa, __get_str(region_name), &__entry->region_uuid
+ __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE),
+ show_comp_id_pldm_flags(__entry->comp_id[0]),
+ show_pldm_entity_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT,
+ CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id),
+ show_pldm_resource_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT,
+ CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id),
+ __entry->hpa, __get_str(region_name), &__entry->region_uuid,
+ show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags), __entry->cme_count
)
);
diff --git a/include/cxl/event.h b/include/cxl/event.h
index e1d485ad376b..2b07adf39010 100644
--- a/include/cxl/event.h
+++ b/include/cxl/event.h
@@ -45,14 +45,17 @@ struct cxl_event_generic {
/*
* General Media Event Record
- * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
+ * CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45
*/
#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
struct cxl_event_gen_media {
struct cxl_event_media_hdr media_hdr;
u8 device[3];
u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
- u8 reserved[46];
+ u8 cme_threshold_ev_flags;
+ u8 cme_count[3];
+ u8 sub_type;
+ u8 reserved[41];
} __packed;
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v5 4/6] cxl/events: Update DRAM Event Record to CXL spec rev 3.1
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
` (2 preceding siblings ...)
2025-01-10 11:55 ` [PATCH v5 3/6] cxl/events: Update General Media Event Record to " shiju.jose
@ 2025-01-10 11:55 ` shiju.jose
2025-01-10 18:27 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 5/6] cxl/events: Update Memory Module " shiju.jose
` (2 subsequent siblings)
6 siblings, 1 reply; 19+ messages in thread
From: shiju.jose @ 2025-01-10 11:55 UTC (permalink / raw)
To: dave.jiang, dan.j.williams, jonathan.cameron, alison.schofield,
nifan.cxl, vishal.l.verma, ira.weiny, dave, linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec 3.1 section 8.2.9.2.1.2 Table 8-46, DRAM Event Record has updated
with following new fields and new types for Memory Event Type, Transaction
Type and Validity Flags fields.
1. Component Identifier
2. Sub-channel
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Memory Error Count at Event
5. Memory Event Sub-Type
Update DRAM events record and DRAM trace event for the above spec
changes. The new fields are inserted in logical places.
Includes trivial consistency of white space improvements.
Example trace print of cxl_dram trace event,
cxl_dram: memdev=mem0 host=0000:0f:00.0 serial=3 log=Informational : \
time=54799339519 uuid=601dcbb3-9c06-4eab-b8af-4e9bfb5c9624 len=128 \
flags='0x1' handle=1 related_handle=0 maint_op_class=1 \
maint_op_sub_class=3 : dpa=18680 dpa_flags='' \
descriptor='UNCORRECTABLE_EVENT|THRESHOLD_EVENT' type='Data Path Error' \
sub_type='Media Link CRC Error' transaction_type='Internal Media Scrub' \
channel=3 rank=17 nibble_mask=3b00b2 bank_group=7 bank=11 row=2 \
column=77 cor_mask=21 00 00 00 00 00 00 00 2c 00 00 00 00 00 00 00 37 00 \
00 00 00 00 00 00 42 00 00 00 00 00 00 00 validity_flags='CHANNEL|RANK|NIBBLE|\
BANK GROUP|BANK|ROW|COLUMN|CORRECTION MASK|COMPONENT|COMPONENT PLDM FORMAT' \
comp_id=01 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
comp_id_pldm_valid_flags='PLDM Entity ID' pldm_entity_id=74 c5 08 9a 1a 0b \
pldm_resource_id=0x00 hpa=ffffffffffffffff region= \
region_uuid=00000000-0000-0000-0000-000000000000 sub_channel=5 \
cme_threshold_ev_flags='Corrected Memory Errors in Multiple Media Components|\
Exceeded Programmable Threshold' cvme_count=148
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
drivers/cxl/core/trace.h | 71 ++++++++++++++++++++++++++++++----------
include/cxl/event.h | 9 +++--
2 files changed, 60 insertions(+), 20 deletions(-)
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index 241c10596f4d..cbaf6244d77f 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -478,7 +478,7 @@ TRACE_EVENT(cxl_general_media,
/*
* DRAM Event Record - DER
*
- * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
+ * CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46
*/
/*
* DRAM Event Record defines many fields the same as the General Media Event
@@ -488,11 +488,17 @@ TRACE_EVENT(cxl_general_media,
#define CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x01
#define CXL_DER_MEM_EVT_TYPE_INV_ADDR 0x02
#define CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x03
-#define show_dram_mem_event_type(type) __print_symbolic(type, \
- { CXL_DER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \
- { CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \
- { CXL_DER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \
- { CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" } \
+#define CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION 0x04
+#define CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE 0x05
+#define CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION 0x06
+#define show_dram_mem_event_type(type) __print_symbolic(type, \
+ { CXL_DER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \
+ { CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \
+ { CXL_DER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \
+ { CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" }, \
+ { CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION, "TE State Violation" }, \
+ { CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE, "Adv Prog CME Counter Expiration" }, \
+ { CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION, "CKID Violation" } \
)
#define CXL_DER_VALID_CHANNEL BIT(0)
@@ -503,15 +509,21 @@ TRACE_EVENT(cxl_general_media,
#define CXL_DER_VALID_ROW BIT(5)
#define CXL_DER_VALID_COLUMN BIT(6)
#define CXL_DER_VALID_CORRECTION_MASK BIT(7)
-#define show_dram_valid_flags(flags) __print_flags(flags, "|", \
- { CXL_DER_VALID_CHANNEL, "CHANNEL" }, \
- { CXL_DER_VALID_RANK, "RANK" }, \
- { CXL_DER_VALID_NIBBLE, "NIBBLE" }, \
- { CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \
- { CXL_DER_VALID_BANK, "BANK" }, \
- { CXL_DER_VALID_ROW, "ROW" }, \
- { CXL_DER_VALID_COLUMN, "COLUMN" }, \
- { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" } \
+#define CXL_DER_VALID_COMPONENT BIT(8)
+#define CXL_DER_VALID_COMPONENT_ID_FORMAT BIT(9)
+#define CXL_DER_VALID_SUB_CHANNEL BIT(10)
+#define show_dram_valid_flags(flags) __print_flags(flags, "|", \
+ { CXL_DER_VALID_CHANNEL, "CHANNEL" }, \
+ { CXL_DER_VALID_RANK, "RANK" }, \
+ { CXL_DER_VALID_NIBBLE, "NIBBLE" }, \
+ { CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \
+ { CXL_DER_VALID_BANK, "BANK" }, \
+ { CXL_DER_VALID_ROW, "ROW" }, \
+ { CXL_DER_VALID_COLUMN, "COLUMN" }, \
+ { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" }, \
+ { CXL_DER_VALID_COMPONENT, "COMPONENT" }, \
+ { CXL_DER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" }, \
+ { CXL_DER_VALID_SUB_CHANNEL, "SUB CHANNEL" } \
)
TRACE_EVENT(cxl_dram,
@@ -527,6 +539,7 @@ TRACE_EVENT(cxl_dram,
__field(u64, dpa)
__field(u8, descriptor)
__field(u8, type)
+ __field(u8, sub_type)
__field(u8, transaction_type)
__field(u8, channel)
__field(u16, validity_flags)
@@ -541,6 +554,10 @@ TRACE_EVENT(cxl_dram,
__field(u8, bank) /* Out of order to pack trace record */
__field(u8, dpa_flags) /* Out of order to pack trace record */
__string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
+ __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
+ __field(u8, sub_channel)
+ __field(u8, cme_threshold_ev_flags)
+ __field(u32, cvme_count)
),
TP_fast_assign(
@@ -553,6 +570,7 @@ TRACE_EVENT(cxl_dram,
__entry->dpa &= CXL_DPA_MASK;
__entry->descriptor = rec->media_hdr.descriptor;
__entry->type = rec->media_hdr.type;
+ __entry->sub_type = rec->sub_type;
__entry->transaction_type = rec->media_hdr.transaction_type;
__entry->validity_flags = get_unaligned_le16(rec->media_hdr.validity_flags);
__entry->channel = rec->media_hdr.channel;
@@ -572,23 +590,40 @@ TRACE_EVENT(cxl_dram,
__assign_str(region_name);
uuid_copy(&__entry->region_uuid, &uuid_null);
}
+ memcpy(__entry->comp_id, &rec->component_id,
+ CXL_EVENT_GEN_MED_COMP_ID_SIZE);
+ __entry->sub_channel = rec->sub_channel;
+ __entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags;
+ __entry->cvme_count = get_unaligned_le24(rec->cvme_count);
),
- CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' " \
+ CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' sub_type='%s' " \
"transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \
"bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \
"validity_flags='%s' " \
- "hpa=%llx region=%s region_uuid=%pUb",
+ "comp_id=%s comp_id_pldm_valid_flags='%s' " \
+ "pldm_entity_id=%s pldm_resource_id=%s " \
+ "hpa=%llx region=%s region_uuid=%pUb " \
+ "sub_channel=%u cme_threshold_ev_flags='%s' cvme_count=%u",
__entry->dpa, show_dpa_flags(__entry->dpa_flags),
show_event_desc_flags(__entry->descriptor),
show_dram_mem_event_type(__entry->type),
+ show_mem_event_sub_type(__entry->sub_type),
show_trans_type(__entry->transaction_type),
__entry->channel, __entry->rank, __entry->nibble_mask,
__entry->bank_group, __entry->bank,
__entry->row, __entry->column,
__print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE),
show_dram_valid_flags(__entry->validity_flags),
- __entry->hpa, __get_str(region_name), &__entry->region_uuid
+ __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE),
+ show_comp_id_pldm_flags(__entry->comp_id[0]),
+ show_pldm_entity_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT,
+ CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id),
+ show_pldm_resource_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT,
+ CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id),
+ __entry->hpa, __get_str(region_name), &__entry->region_uuid,
+ __entry->sub_channel, show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags),
+ __entry->cvme_count
)
);
diff --git a/include/cxl/event.h b/include/cxl/event.h
index 2b07adf39010..10815414f376 100644
--- a/include/cxl/event.h
+++ b/include/cxl/event.h
@@ -60,7 +60,7 @@ struct cxl_event_gen_media {
/*
* DRAM Event Record - DER
- * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
+ * CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46
*/
#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
struct cxl_event_dram {
@@ -71,7 +71,12 @@ struct cxl_event_dram {
u8 row[3];
u8 column[2];
u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
- u8 reserved[0x17];
+ u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ u8 sub_channel;
+ u8 cme_threshold_ev_flags;
+ u8 cvme_count[3];
+ u8 sub_type;
+ u8 reserved;
} __packed;
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v5 5/6] cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
` (3 preceding siblings ...)
2025-01-10 11:55 ` [PATCH v5 4/6] cxl/events: Update DRAM " shiju.jose
@ 2025-01-10 11:55 ` shiju.jose
2025-01-10 18:46 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 6/6] cxl/test: Update test code for event records " shiju.jose
2025-01-10 16:06 ` [PATCH v5 0/6] Update Event Records " Jonathan Cameron
6 siblings, 1 reply; 19+ messages in thread
From: shiju.jose @ 2025-01-10 11:55 UTC (permalink / raw)
To: dave.jiang, dan.j.williams, jonathan.cameron, alison.schofield,
nifan.cxl, vishal.l.verma, ira.weiny, dave, linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec 3.1 section 8.2.9.2.1.3 Table 8-47, Memory Module Event Record
has updated with following new fields and new info for Device Event Type
and Device Health Information fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Update the Memory Module event record and Memory Module trace event for
the above spec changes. The new fields are inserted in logical places.
Example trace print of cxl_memory_module trace event,
cxl_memory_module: memdev=mem3 host=0000:0f:00.0 serial=3 log=Fatal : \
time=371709344709 uuid=fe927475-dd59-4339-a586-79bab113b774 len=128 \
flags='0x1' handle=2 related_handle=0 maint_op_class=0 \
maint_op_sub_class=0 : event_type='Temperature Change' \
event_sub_type='Unsupported Config Data' \
health_status='MAINTENANCE_NEEDED|REPLACEMENT_NEEDED' \
media_status='All Data Loss in Event of Power Loss' as_life_used=0x3 \
as_dev_temp=Normal as_cor_vol_err_cnt=Normal as_cor_per_err_cnt=Normal \
life_used=8 device_temp=3 dirty_shutdown_cnt=33 cor_vol_err_cnt=25 \
cor_per_err_cnt=45 validity_flags='COMPONENT|COMPONENT PLDM FORMAT' \
comp_id=03 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
comp_id_pldm_valid_flags='Resource ID' \
pldm_entity_id=0x00 pldm_resource_id=fc d2 7e 2f
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
drivers/cxl/core/trace.h | 62 ++++++++++++++++++++++++++++++++++------
include/cxl/event.h | 9 ++++--
2 files changed, 60 insertions(+), 11 deletions(-)
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index cbaf6244d77f..40cc3a7f4402 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -630,7 +630,7 @@ TRACE_EVENT(cxl_dram,
/*
* Memory Module Event Record - MMER
*
- * CXL res 3.0 section 8.2.9.2.1.3; Table 8-45
+ * CXL res 3.1 section 8.2.9.2.1.3; Table 8-47
*/
#define CXL_MMER_HEALTH_STATUS_CHANGE 0x00
#define CXL_MMER_MEDIA_STATUS_CHANGE 0x01
@@ -638,27 +638,35 @@ TRACE_EVENT(cxl_dram,
#define CXL_MMER_TEMP_CHANGE 0x03
#define CXL_MMER_DATA_PATH_ERROR 0x04
#define CXL_MMER_LSA_ERROR 0x05
+#define CXL_MMER_UNRECOV_SIDEBAND_BUS_ERROR 0x06
+#define CXL_MMER_MEMORY_MEDIA_FRU_ERROR 0x07
+#define CXL_MMER_POWER_MANAGEMENT_FAULT 0x08
#define show_dev_evt_type(type) __print_symbolic(type, \
{ CXL_MMER_HEALTH_STATUS_CHANGE, "Health Status Change" }, \
{ CXL_MMER_MEDIA_STATUS_CHANGE, "Media Status Change" }, \
{ CXL_MMER_LIFE_USED_CHANGE, "Life Used Change" }, \
{ CXL_MMER_TEMP_CHANGE, "Temperature Change" }, \
{ CXL_MMER_DATA_PATH_ERROR, "Data Path Error" }, \
- { CXL_MMER_LSA_ERROR, "LSA Error" } \
+ { CXL_MMER_LSA_ERROR, "LSA Error" }, \
+ { CXL_MMER_UNRECOV_SIDEBAND_BUS_ERROR, "Unrecoverable Internal Sideband Bus Error" }, \
+ { CXL_MMER_MEMORY_MEDIA_FRU_ERROR, "Memory Media FRU Error" }, \
+ { CXL_MMER_POWER_MANAGEMENT_FAULT, "Power Management Fault" } \
)
/*
* Device Health Information - DHI
*
- * CXL res 3.0 section 8.2.9.8.3.1; Table 8-100
+ * CXL res 3.1 section 8.2.9.9.3.1; Table 8-133
*/
#define CXL_DHI_HS_MAINTENANCE_NEEDED BIT(0)
#define CXL_DHI_HS_PERFORMANCE_DEGRADED BIT(1)
#define CXL_DHI_HS_HW_REPLACEMENT_NEEDED BIT(2)
+#define CXL_DHI_HS_MEM_CAPACITY_DEGRADED BIT(3)
#define show_health_status_flags(flags) __print_flags(flags, "|", \
{ CXL_DHI_HS_MAINTENANCE_NEEDED, "MAINTENANCE_NEEDED" }, \
{ CXL_DHI_HS_PERFORMANCE_DEGRADED, "PERFORMANCE_DEGRADED" }, \
- { CXL_DHI_HS_HW_REPLACEMENT_NEEDED, "REPLACEMENT_NEEDED" } \
+ { CXL_DHI_HS_HW_REPLACEMENT_NEEDED, "REPLACEMENT_NEEDED" }, \
+ { CXL_DHI_HS_MEM_CAPACITY_DEGRADED, "MEM_CAPACITY_DEGRADED" } \
)
#define CXL_DHI_MS_NORMAL 0x00
@@ -712,6 +720,26 @@ TRACE_EVENT(cxl_dram,
#define CXL_DHI_AS_COR_VOL_ERR_CNT(as) ((as & 0x10) >> 4)
#define CXL_DHI_AS_COR_PER_ERR_CNT(as) ((as & 0x20) >> 5)
+#define CXL_MMER_VALID_COMPONENT BIT(0)
+#define CXL_MMER_VALID_COMPONENT_ID_FORMAT BIT(1)
+#define show_mem_module_valid_flags(flags) __print_flags(flags, "|", \
+ { CXL_MMER_VALID_COMPONENT, "COMPONENT" }, \
+ { CXL_MMER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" } \
+)
+#define CXL_MMER_DEV_EVT_SUB_TYPE_NOT_REPORTED 0x00
+#define CXL_MMER_DEV_EVT_SUB_TYPE_INVALID_CONFIG_DATA 0x01
+#define CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_CONFIG_DATA 0x02
+#define CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_MEM_MEDIA_FRU 0x03
+#define show_dev_event_sub_type(sub_type) __print_symbolic(sub_type, \
+ { CXL_MMER_DEV_EVT_SUB_TYPE_NOT_REPORTED, "Not Reported" }, \
+ { CXL_MMER_DEV_EVT_SUB_TYPE_INVALID_CONFIG_DATA, "Invalid Config Data" }, \
+ { CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_CONFIG_DATA, "Unsupported Config Data" }, \
+ { \
+ CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_MEM_MEDIA_FRU, \
+ "Unsupported Memory Media FRU" \
+ } \
+)
+
TRACE_EVENT(cxl_memory_module,
TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log,
@@ -724,6 +752,7 @@ TRACE_EVENT(cxl_memory_module,
/* Memory Module Event */
__field(u8, event_type)
+ __field(u8, event_sub_type)
/* Device Health Info */
__field(u8, health_status)
@@ -734,6 +763,8 @@ TRACE_EVENT(cxl_memory_module,
__field(u32, cor_per_err_cnt)
__field(s16, device_temp)
__field(u8, add_status)
+ __field(u16, validity_flags)
+ __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
),
TP_fast_assign(
@@ -742,6 +773,7 @@ TRACE_EVENT(cxl_memory_module,
/* Memory Module Event */
__entry->event_type = rec->event_type;
+ __entry->event_sub_type = rec->event_sub_type;
/* Device Health Info */
__entry->health_status = rec->info.health_status;
@@ -752,13 +784,20 @@ TRACE_EVENT(cxl_memory_module,
__entry->cor_per_err_cnt = get_unaligned_le32(rec->info.cor_per_err_cnt);
__entry->device_temp = get_unaligned_le16(rec->info.device_temp);
__entry->add_status = rec->info.add_status;
+ __entry->validity_flags = get_unaligned_le16(rec->validity_flags);
+ memcpy(__entry->comp_id, &rec->component_id,
+ CXL_EVENT_GEN_MED_COMP_ID_SIZE);
),
- CXL_EVT_TP_printk("event_type='%s' health_status='%s' media_status='%s' " \
- "as_life_used=%s as_dev_temp=%s as_cor_vol_err_cnt=%s " \
+ CXL_EVT_TP_printk("event_type='%s' event_sub_type='%s' health_status='%s' " \
+ "media_status='%s' as_life_used=%s as_dev_temp=%s as_cor_vol_err_cnt=%s " \
"as_cor_per_err_cnt=%s life_used=%u device_temp=%d " \
- "dirty_shutdown_cnt=%u cor_vol_err_cnt=%u cor_per_err_cnt=%u",
+ "dirty_shutdown_cnt=%u cor_vol_err_cnt=%u cor_per_err_cnt=%u " \
+ "validity_flags='%s' " \
+ "comp_id=%s comp_id_pldm_valid_flags='%s' " \
+ "pldm_entity_id=%s pldm_resource_id=%s",
show_dev_evt_type(__entry->event_type),
+ show_dev_event_sub_type(__entry->event_sub_type),
show_health_status_flags(__entry->health_status),
show_media_status(__entry->media_status),
show_two_bit_status(CXL_DHI_AS_LIFE_USED(__entry->add_status)),
@@ -767,7 +806,14 @@ TRACE_EVENT(cxl_memory_module,
show_one_bit_status(CXL_DHI_AS_COR_PER_ERR_CNT(__entry->add_status)),
__entry->life_used, __entry->device_temp,
__entry->dirty_shutdown_cnt, __entry->cor_vol_err_cnt,
- __entry->cor_per_err_cnt
+ __entry->cor_per_err_cnt,
+ show_mem_module_valid_flags(__entry->validity_flags),
+ __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE),
+ show_comp_id_pldm_flags(__entry->comp_id[0]),
+ show_pldm_entity_id(__entry->validity_flags, CXL_MMER_VALID_COMPONENT,
+ CXL_MMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id),
+ show_pldm_resource_id(__entry->validity_flags, CXL_MMER_VALID_COMPONENT,
+ CXL_MMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id)
)
);
diff --git a/include/cxl/event.h b/include/cxl/event.h
index 10815414f376..04edd44bd26f 100644
--- a/include/cxl/event.h
+++ b/include/cxl/event.h
@@ -81,7 +81,7 @@ struct cxl_event_dram {
/*
* Get Health Info Record
- * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
+ * CXL rev 3.1 section 8.2.9.9.3.1; Table 8-133
*/
struct cxl_get_health_info {
u8 health_status;
@@ -96,13 +96,16 @@ struct cxl_get_health_info {
/*
* Memory Module Event Record
- * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
+ * CXL rev 3.1 section 8.2.9.2.1.3; Table 8-47
*/
struct cxl_event_mem_module {
struct cxl_event_record_hdr hdr;
u8 event_type;
struct cxl_get_health_info info;
- u8 reserved[0x3d];
+ u8 validity_flags[2];
+ u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ u8 event_sub_type;
+ u8 reserved[0x2a];
} __packed;
union cxl_event {
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v5 6/6] cxl/test: Update test code for event records to CXL spec rev 3.1
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
` (4 preceding siblings ...)
2025-01-10 11:55 ` [PATCH v5 5/6] cxl/events: Update Memory Module " shiju.jose
@ 2025-01-10 11:55 ` shiju.jose
2025-01-10 18:48 ` Ira Weiny
2025-01-10 16:06 ` [PATCH v5 0/6] Update Event Records " Jonathan Cameron
6 siblings, 1 reply; 19+ messages in thread
From: shiju.jose @ 2025-01-10 11:55 UTC (permalink / raw)
To: dave.jiang, dan.j.williams, jonathan.cameron, alison.schofield,
nifan.cxl, vishal.l.verma, ira.weiny, dave, linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
Update test code for General Media, DRAM, Memory Module Event
Records to CXL spec rev 3.1.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
tools/testing/cxl/test/mem.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
index 347c1e7b37bd..8d731bd63988 100644
--- a/tools/testing/cxl/test/mem.c
+++ b/tools/testing/cxl/test/mem.c
@@ -401,6 +401,10 @@ struct cxl_test_gen_media gen_media = {
.channel = 1,
.rank = 30,
},
+ .component_id = { 0x3, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d },
+ .cme_threshold_ev_flags = 3,
+ .cme_count = { 33, 0, 0 },
+ .sub_type = 0x2,
},
};
@@ -429,6 +433,11 @@ struct cxl_test_dram dram = {
.bank_group = 5,
.bank = 2,
.column = {0xDE, 0xAD},
+ .component_id = { 0x1, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d },
+ .sub_channel = 8,
+ .cme_threshold_ev_flags = 2,
+ .cvme_count = { 14, 0, 0 },
+ .sub_type = 0x5,
},
};
@@ -456,7 +465,10 @@ struct cxl_test_mem_module mem_module = {
.dirty_shutdown_cnt = { 0xde, 0xad, 0xbe, 0xef },
.cor_vol_err_cnt = { 0xde, 0xad, 0xbe, 0xef },
.cor_per_err_cnt = { 0xde, 0xad, 0xbe, 0xef },
- }
+ },
+ /* .validity_flags = <set below> */
+ .component_id = { 0x2, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d },
+ .event_sub_type = 0x3,
},
};
@@ -478,13 +490,18 @@ static int mock_set_timestamp(struct cxl_dev_state *cxlds,
static void cxl_mock_add_event_logs(struct mock_event_store *mes)
{
- put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK,
+ put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK |
+ CXL_GMER_VALID_COMPONENT | CXL_GMER_VALID_COMPONENT_ID_FORMAT,
&gen_media.rec.media_hdr.validity_flags);
put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP |
- CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN,
+ CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN | CXL_DER_VALID_SUB_CHANNEL |
+ CXL_DER_VALID_COMPONENT | CXL_DER_VALID_COMPONENT_ID_FORMAT,
&dram.rec.media_hdr.validity_flags);
+ put_unaligned_le16(CXL_MMER_VALID_COMPONENT | CXL_MMER_VALID_COMPONENT_ID_FORMAT,
+ &mem_module.rec.validity_flags);
+
mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed);
mes_add_event(mes, CXL_EVENT_TYPE_INFO,
(struct cxl_event_record_raw *)&gen_media);
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
` (5 preceding siblings ...)
2025-01-10 11:55 ` [PATCH v5 6/6] cxl/test: Update test code for event records " shiju.jose
@ 2025-01-10 16:06 ` Jonathan Cameron
2025-01-10 16:46 ` Shiju Jose
6 siblings, 1 reply; 19+ messages in thread
From: Jonathan Cameron @ 2025-01-10 16:06 UTC (permalink / raw)
To: shiju.jose
Cc: dave.jiang, dan.j.williams, alison.schofield, nifan.cxl,
vishal.l.verma, ira.weiny, dave, linux-cxl, linux-kernel,
linuxarm, tanxiaofei, prime.zeng
On Fri, 10 Jan 2025 11:55:50 +0000
<shiju.jose@huawei.com> wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> Add updates in the CXL events records and CXL trace events implementations
> for the changes in CXL spec rev 3.1.
>
> Shiju Jose (6):
> cxl/events: Update Common Event Record to CXL spec rev 3.1
> cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
> cxl/events: Update General Media Event Record to CXL spec rev 3.1
> cxl/events: Update DRAM Event Record to CXL spec rev 3.1
> cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
> cxl/test: Update test code for event records to CXL spec rev 3.1
>
> Changes:
> V4 -> V5
> 1. Reverted changes made in v4 for overcoming parsing error when
> libtraceevent in userspace parses the CXL trace events, for rasdaemon.
> This was due to trace event's format file is larger than PAGE_SIZE, not
> supported reading complete format file in one go in the kernel and thus
> fixed in the rasdaemon.
Great to see that resolved.
> 2. Rebased to v6.13-rc5.
Should probably say why when doing a rebase to something other than rc1.
In this case this is what cxl.git/next is based on after some fixes earlier
in the cycle so a sensible choice for this set.
As far as I'm concerned this set is ready to go, but more eyes always good
if anyone has time! Same for the ras-daemon series once this is queued for
the kernel.
Jonathan
> 3. Tested with rasdaemon and ras-mc-ctl tools updated for CXL spec rev 3.1
> event record changes.
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1
2025-01-10 16:06 ` [PATCH v5 0/6] Update Event Records " Jonathan Cameron
@ 2025-01-10 16:46 ` Shiju Jose
2025-01-10 20:18 ` Dave Jiang
0 siblings, 1 reply; 19+ messages in thread
From: Shiju Jose @ 2025-01-10 16:46 UTC (permalink / raw)
To: Jonathan Cameron
Cc: dave.jiang@intel.com, dan.j.williams@intel.com,
alison.schofield@intel.com, nifan.cxl@gmail.com,
vishal.l.verma@intel.com, ira.weiny@intel.com, dave@stgolabs.net,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Linuxarm,
tanxiaofei, Zengtao (B)
>-----Original Message-----
>From: Jonathan Cameron <jonathan.cameron@huawei.com>
>Sent: 10 January 2025 16:07
>To: Shiju Jose <shiju.jose@huawei.com>
>Cc: dave.jiang@intel.com; dan.j.williams@intel.com; alison.schofield@intel.com;
>nifan.cxl@gmail.com; vishal.l.verma@intel.com; ira.weiny@intel.com;
>dave@stgolabs.net; linux-cxl@vger.kernel.org; linux-kernel@vger.kernel.org;
>Linuxarm <linuxarm@huawei.com>; tanxiaofei <tanxiaofei@huawei.com>;
>Zengtao (B) <prime.zeng@hisilicon.com>
>Subject: Re: [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1
>
>On Fri, 10 Jan 2025 11:55:50 +0000
><shiju.jose@huawei.com> wrote:
>
>> From: Shiju Jose <shiju.jose@huawei.com>
>>
>> Add updates in the CXL events records and CXL trace events
>> implementations for the changes in CXL spec rev 3.1.
>>
>> Shiju Jose (6):
>> cxl/events: Update Common Event Record to CXL spec rev 3.1
>> cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
>> cxl/events: Update General Media Event Record to CXL spec rev 3.1
>> cxl/events: Update DRAM Event Record to CXL spec rev 3.1
>> cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
>> cxl/test: Update test code for event records to CXL spec rev 3.1
>>
>> Changes:
>> V4 -> V5
>> 1. Reverted changes made in v4 for overcoming parsing error when
>> libtraceevent in userspace parses the CXL trace events, for rasdaemon.
>> This was due to trace event's format file is larger than PAGE_SIZE,
>> not supported reading complete format file in one go in the kernel and
>> thus fixed in the rasdaemon.
>
>Great to see that resolved.
>
>> 2. Rebased to v6.13-rc5.
>
>Should probably say why when doing a rebase to something other than rc1.
>In this case this is what cxl.git/next is based on after some fixes earlier in the
>cycle so a sensible choice for this set.
I checked. These patches applied cleanly in cxl.git/next and buid okay.
Thanks,
Shiju
>
>As far as I'm concerned this set is ready to go, but more eyes always good if
>anyone has time! Same for the ras-daemon series once this is queued for the
>kernel.
>
>Jonathan
>
>> 3. Tested with rasdaemon and ras-mc-ctl tools updated for CXL spec rev 3.1
>> event record changes.
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 1/6] cxl/events: Update Common Event Record to CXL spec rev 3.1
2025-01-10 11:55 ` [PATCH v5 1/6] cxl/events: Update Common Event Record " shiju.jose
@ 2025-01-10 17:35 ` Ira Weiny
0 siblings, 0 replies; 19+ messages in thread
From: Ira Weiny @ 2025-01-10 17:35 UTC (permalink / raw)
To: shiju.jose, dave.jiang, dan.j.williams, jonathan.cameron,
alison.schofield, nifan.cxl, vishal.l.verma, ira.weiny, dave,
linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec 3.1 section 8.2.9.2.1 Table 8-42, Common Event Record format has
> updated with Maintenance Operation Subclass information.
>
> Add updates for the above spec change in the CXL events record and CXL
> common trace event implementations.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
[snip]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 2/6] cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
2025-01-10 11:55 ` [PATCH v5 2/6] cxl/events: Add Component Identifier formatting for " shiju.jose
@ 2025-01-10 17:43 ` Ira Weiny
0 siblings, 0 replies; 19+ messages in thread
From: Ira Weiny @ 2025-01-10 17:43 UTC (permalink / raw)
To: shiju.jose, dave.jiang, dan.j.williams, jonathan.cameron,
alison.schofield, nifan.cxl, vishal.l.verma, ira.weiny, dave,
linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> Add Component Identifier formatting for CXL spec rev 3.1, Section
> 8.2.9.2.1, Table 8-44.
>
> Examples for Component Identifier format in trace log,
>
> validity_flags='CHANNEL|RANK|DEVICE|COMPONENT|COMPONENT PLDM FORMAT' \
> comp_id=03 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
> comp_id_pldm_valid_flags='PLDM Entity ID | Resource ID' \
> pldm_entity_id=74 c5 08 9a 1a 0b pldm_resource_id=fc d2 7e 2f \
>
> validity_flags='COMPONENT|COMPONENT PLDM FORMAT' \
> comp_id=02 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
> comp_id_pldm_valid_flags='Resource ID' \
> pldm_entity_id=0x00 pldm_resource_id=fc d2 7e 2f
>
> If the validity flags for component ID/component ID format or PLDM ID or
> resource ID are not set, then pldm_entity_id=0x00 or pldm_resource_id=0x00
> would be printed.
NIT: I would have mentioned that these are used in subsequent patches...
But...
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
[snip]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 3/6] cxl/events: Update General Media Event Record to CXL spec rev 3.1
2025-01-10 11:55 ` [PATCH v5 3/6] cxl/events: Update General Media Event Record to " shiju.jose
@ 2025-01-10 17:54 ` Ira Weiny
2025-01-10 18:30 ` Ira Weiny
1 sibling, 0 replies; 19+ messages in thread
From: Ira Weiny @ 2025-01-10 17:54 UTC (permalink / raw)
To: shiju.jose, dave.jiang, dan.j.williams, jonathan.cameron,
alison.schofield, nifan.cxl, vishal.l.verma, ira.weiny, dave,
linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev 3.1 section 8.2.9.2.1.1 Table 8-45, General Media Event
> Record has updated with following new fields and new types for Memory
> Event Type and Transaction Type fields.
> 1. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 2. Corrected Memory Error Count at Event
> 3. Memory Event Sub-Type
>
> The format of component identifier has changed (CXL spec 3.1 section
> 8.2.9.2.1 Table 8-44).
>
> Update the general media event record and general media trace event for
> the above spec changes. The new fields are inserted in logical places.
>
> Example trace log of cxl_general_media trace event,
>
> cxl_general_media: memdev=mem0 host=0000:0f:00.0 serial=3 log=Fatal : \
> time=156831237413 uuid=fbcd0a77-c260-417f-85a9-088b1621eba6 len=128 \
> flags='0x1' handle=1 related_handle=0 maint_op_class=2 \
> maint_op_sub_class=4 : dpa=30d40 dpa_flags='' \
> descriptor='UNCORRECTABLE_EVENT|THRESHOLD_EVENT|POISON_LIST_OVERFLOW' \
> type='TE State Violation' sub_type='Media Link Command Training Error' \
> transaction_type='Host Inject Poison' channel=3 rank=33 device=5 \
> validity_flags='CHANNEL|RANK|DEVICE|COMPONENT|COMPONENT PLDM FORMAT' \
> comp_id=03 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
> comp_id_pldm_valid_flags='PLDM Entity ID | Resource ID' \
> pldm_entity_id=74 c5 08 9a 1a 0b pldm_resource_id=fc d2 7e 2f \
> hpa=ffffffffffffffff region= \
> region_uuid=00000000-0000-0000-0000-000000000000 \
> cme_threshold_ev_flags='Corrected Memory Errors in Multiple Media \
> Components|Exceeded Programmable Threshold' cme_count=120
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
[snip]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 4/6] cxl/events: Update DRAM Event Record to CXL spec rev 3.1
2025-01-10 11:55 ` [PATCH v5 4/6] cxl/events: Update DRAM " shiju.jose
@ 2025-01-10 18:27 ` Ira Weiny
2025-01-11 9:16 ` Shiju Jose
0 siblings, 1 reply; 19+ messages in thread
From: Ira Weiny @ 2025-01-10 18:27 UTC (permalink / raw)
To: shiju.jose, dave.jiang, dan.j.williams, jonathan.cameron,
alison.schofield, nifan.cxl, vishal.l.verma, ira.weiny, dave,
linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
[snip]
>
> TRACE_EVENT(cxl_dram,
> @@ -527,6 +539,7 @@ TRACE_EVENT(cxl_dram,
> __field(u64, dpa)
> __field(u8, descriptor)
> __field(u8, type)
> + __field(u8, sub_type)
I just noticed this with the previous patch too. To pack the record this
should be below...
> __field(u8, transaction_type)
> __field(u8, channel)
> __field(u16, validity_flags)
> @@ -541,6 +554,10 @@ TRACE_EVENT(cxl_dram,
> __field(u8, bank) /* Out of order to pack trace record */
> __field(u8, dpa_flags) /* Out of order to pack trace record */
Here.
> __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
> + __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
> + __field(u8, sub_channel)
> + __field(u8, cme_threshold_ev_flags)
> + __field(u32, cvme_count)
> ),
And these reordered too. Like this:
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index cbaf6244d77f..6f4bf4925cbf 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -539,7 +539,6 @@ TRACE_EVENT(cxl_dram,
__field(u64, dpa)
__field(u8, descriptor)
__field(u8, type)
- __field(u8, sub_type)
__field(u8, transaction_type)
__field(u8, channel)
__field(u16, validity_flags)
@@ -553,11 +552,13 @@ TRACE_EVENT(cxl_dram,
__field(u8, bank_group) /* Out of order to pack trace record */
__field(u8, bank) /* Out of order to pack trace record */
__field(u8, dpa_flags) /* Out of order to pack trace record */
- __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
+ /* The following are out of order to pack the trace record */
__array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
+ __field(u32, cvme_count)
+ __field(u8, sub_type)
__field(u8, sub_channel)
__field(u8, cme_threshold_ev_flags)
- __field(u32, cvme_count)
+ __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
),
TP_fast_assign(
Other than that it looks good. Perhaps Dave can just squash this hunk?
Ira
[snip]
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v5 3/6] cxl/events: Update General Media Event Record to CXL spec rev 3.1
2025-01-10 11:55 ` [PATCH v5 3/6] cxl/events: Update General Media Event Record to " shiju.jose
2025-01-10 17:54 ` Ira Weiny
@ 2025-01-10 18:30 ` Ira Weiny
1 sibling, 0 replies; 19+ messages in thread
From: Ira Weiny @ 2025-01-10 18:30 UTC (permalink / raw)
To: shiju.jose, dave.jiang, dan.j.williams, jonathan.cameron,
alison.schofield, nifan.cxl, vishal.l.verma, ira.weiny, dave,
linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
[snip]
>
> TRACE_EVENT(cxl_general_media,
> @@ -353,6 +402,7 @@ TRACE_EVENT(cxl_general_media,
> __field(u64, dpa)
> __field(u8, descriptor)
> __field(u8, type)
> + __field(u8, sub_type)
> __field(u8, transaction_type)
> __field(u8, channel)
> __field(u32, device)
> @@ -364,6 +414,8 @@ TRACE_EVENT(cxl_general_media,
> __field(u8, rank)
> __field(u8, dpa_flags)
> __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
> + __field(u8, cme_threshold_ev_flags)
> + __field(u32, cme_count)
> ),
>
Reorder these as well to pack the record.
Ira
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index 241c10596f4d..39e83b8543f3 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -402,7 +402,6 @@ TRACE_EVENT(cxl_general_media,
__field(u64, dpa)
__field(u8, descriptor)
__field(u8, type)
- __field(u8, sub_type)
__field(u8, transaction_type)
__field(u8, channel)
__field(u32, device)
@@ -413,9 +412,10 @@ TRACE_EVENT(cxl_general_media,
__field(u16, validity_flags)
__field(u8, rank)
__field(u8, dpa_flags)
- __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
- __field(u8, cme_threshold_ev_flags)
__field(u32, cme_count)
+ __field(u8, sub_type)
+ __field(u8, cme_threshold_ev_flags)
+ __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
),
TP_fast_assign(
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v5 5/6] cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
2025-01-10 11:55 ` [PATCH v5 5/6] cxl/events: Update Memory Module " shiju.jose
@ 2025-01-10 18:46 ` Ira Weiny
0 siblings, 0 replies; 19+ messages in thread
From: Ira Weiny @ 2025-01-10 18:46 UTC (permalink / raw)
To: shiju.jose, dave.jiang, dan.j.williams, jonathan.cameron,
alison.schofield, nifan.cxl, vishal.l.verma, ira.weiny, dave,
linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
[snip]
> @@ -724,6 +752,7 @@ TRACE_EVENT(cxl_memory_module,
>
> /* Memory Module Event */
> __field(u8, event_type)
> + __field(u8, event_sub_type)
>
> /* Device Health Info */
> __field(u8, health_status)
> @@ -734,6 +763,8 @@ TRACE_EVENT(cxl_memory_module,
> __field(u32, cor_per_err_cnt)
> __field(s16, device_temp)
> __field(u8, add_status)
> + __field(u16, validity_flags)
> + __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
> ),
With the change of the packing of the record.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index cfb8de6f9739..5989e5f9f38d 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -753,7 +753,6 @@ TRACE_EVENT(cxl_memory_module,
/* Memory Module Event */
__field(u8, event_type)
- __field(u8, event_sub_type)
/* Device Health Info */
__field(u8, health_status)
@@ -764,8 +763,9 @@ TRACE_EVENT(cxl_memory_module,
__field(u32, cor_per_err_cnt)
__field(s16, device_temp)
__field(u8, add_status)
- __field(u16, validity_flags)
+ __field(u8, event_sub_type)
__array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
+ __field(u16, validity_flags)
),
TP_fast_assign(
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v5 6/6] cxl/test: Update test code for event records to CXL spec rev 3.1
2025-01-10 11:55 ` [PATCH v5 6/6] cxl/test: Update test code for event records " shiju.jose
@ 2025-01-10 18:48 ` Ira Weiny
0 siblings, 0 replies; 19+ messages in thread
From: Ira Weiny @ 2025-01-10 18:48 UTC (permalink / raw)
To: shiju.jose, dave.jiang, dan.j.williams, jonathan.cameron,
alison.schofield, nifan.cxl, vishal.l.verma, ira.weiny, dave,
linux-cxl
Cc: linux-kernel, linuxarm, tanxiaofei, prime.zeng, shiju.jose
shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> Update test code for General Media, DRAM, Memory Module Event
> Records to CXL spec rev 3.1.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
[snip]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1
2025-01-10 16:46 ` Shiju Jose
@ 2025-01-10 20:18 ` Dave Jiang
2025-01-11 9:22 ` Shiju Jose
0 siblings, 1 reply; 19+ messages in thread
From: Dave Jiang @ 2025-01-10 20:18 UTC (permalink / raw)
To: Shiju Jose, Jonathan Cameron
Cc: dan.j.williams@intel.com, alison.schofield@intel.com,
nifan.cxl@gmail.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, dave@stgolabs.net, linux-cxl@vger.kernel.org,
linux-kernel@vger.kernel.org, Linuxarm, tanxiaofei, Zengtao (B)
On 1/10/25 9:46 AM, Shiju Jose wrote:
>> -----Original Message-----
>> From: Jonathan Cameron <jonathan.cameron@huawei.com>
>> Sent: 10 January 2025 16:07
>> To: Shiju Jose <shiju.jose@huawei.com>
>> Cc: dave.jiang@intel.com; dan.j.williams@intel.com; alison.schofield@intel.com;
>> nifan.cxl@gmail.com; vishal.l.verma@intel.com; ira.weiny@intel.com;
>> dave@stgolabs.net; linux-cxl@vger.kernel.org; linux-kernel@vger.kernel.org;
>> Linuxarm <linuxarm@huawei.com>; tanxiaofei <tanxiaofei@huawei.com>;
>> Zengtao (B) <prime.zeng@hisilicon.com>
>> Subject: Re: [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1
>>
>> On Fri, 10 Jan 2025 11:55:50 +0000
>> <shiju.jose@huawei.com> wrote:
>>
>>> From: Shiju Jose <shiju.jose@huawei.com>
>>>
>>> Add updates in the CXL events records and CXL trace events
>>> implementations for the changes in CXL spec rev 3.1.
>>>
>>> Shiju Jose (6):
>>> cxl/events: Update Common Event Record to CXL spec rev 3.1
>>> cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
>>> cxl/events: Update General Media Event Record to CXL spec rev 3.1
>>> cxl/events: Update DRAM Event Record to CXL spec rev 3.1
>>> cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
>>> cxl/test: Update test code for event records to CXL spec rev 3.1
>>>
>>> Changes:
>>> V4 -> V5
>>> 1. Reverted changes made in v4 for overcoming parsing error when
>>> libtraceevent in userspace parses the CXL trace events, for rasdaemon.
>>> This was due to trace event's format file is larger than PAGE_SIZE,
>>> not supported reading complete format file in one go in the kernel and
>>> thus fixed in the rasdaemon.
>>
>> Great to see that resolved.
>>
>>> 2. Rebased to v6.13-rc5.
>>
>> Should probably say why when doing a rebase to something other than rc1.
>> In this case this is what cxl.git/next is based on after some fixes earlier in the
>> cycle so a sensible choice for this set.
>
> I checked. These patches applied cleanly in cxl.git/next and buid okay.
Hi Shiju,
Can you please apply Ira's suggestions and respin a v6? Thanks!
>
> Thanks,
> Shiju
>>
>> As far as I'm concerned this set is ready to go, but more eyes always good if
>> anyone has time! Same for the ras-daemon series once this is queued for the
>> kernel.
>>
>> Jonathan
>>
>>> 3. Tested with rasdaemon and ras-mc-ctl tools updated for CXL spec rev 3.1
>>> event record changes.
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v5 4/6] cxl/events: Update DRAM Event Record to CXL spec rev 3.1
2025-01-10 18:27 ` Ira Weiny
@ 2025-01-11 9:16 ` Shiju Jose
0 siblings, 0 replies; 19+ messages in thread
From: Shiju Jose @ 2025-01-11 9:16 UTC (permalink / raw)
To: Ira Weiny, dave.jiang@intel.com, dan.j.williams@intel.com,
Jonathan Cameron, alison.schofield@intel.com, nifan.cxl@gmail.com,
vishal.l.verma@intel.com, dave@stgolabs.net,
linux-cxl@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, Linuxarm, tanxiaofei, Zengtao (B)
>-----Original Message-----
>From: Ira Weiny <ira.weiny@intel.com>
>Sent: 10 January 2025 18:27
>To: Shiju Jose <shiju.jose@huawei.com>; dave.jiang@intel.com;
>dan.j.williams@intel.com; Jonathan Cameron
><jonathan.cameron@huawei.com>; alison.schofield@intel.com;
>nifan.cxl@gmail.com; vishal.l.verma@intel.com; ira.weiny@intel.com;
>dave@stgolabs.net; linux-cxl@vger.kernel.org
>Cc: linux-kernel@vger.kernel.org; Linuxarm <linuxarm@huawei.com>;
>tanxiaofei <tanxiaofei@huawei.com>; Zengtao (B) <prime.zeng@hisilicon.com>;
>Shiju Jose <shiju.jose@huawei.com>
>Subject: Re: [PATCH v5 4/6] cxl/events: Update DRAM Event Record to CXL spec
>rev 3.1
>
>shiju.jose@ wrote:
>> From: Shiju Jose <shiju.jose@huawei.com>
>>
>
>[snip]
>
>>
>> TRACE_EVENT(cxl_dram,
>> @@ -527,6 +539,7 @@ TRACE_EVENT(cxl_dram,
>> __field(u64, dpa)
>> __field(u8, descriptor)
>> __field(u8, type)
>> + __field(u8, sub_type)
>
>I just noticed this with the previous patch too. To pack the record this should be
>below...
Hi Ira,
Thanks for reviewing and for the feedbacks.
I have modified for your suggestions and will be in the v6.
Thanks,
Shiju
>
>> __field(u8, transaction_type)
>> __field(u8, channel)
>> __field(u16, validity_flags)
>> @@ -541,6 +554,10 @@ TRACE_EVENT(cxl_dram,
>> __field(u8, bank) /* Out of order to pack trace record */
>> __field(u8, dpa_flags) /* Out of order to pack trace record */
>
>Here.
>
>> __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
>> + __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
>> + __field(u8, sub_channel)
>> + __field(u8, cme_threshold_ev_flags)
>> + __field(u32, cvme_count)
>> ),
>
>And these reordered too. Like this:
>
>diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index
>cbaf6244d77f..6f4bf4925cbf 100644
>--- a/drivers/cxl/core/trace.h
>+++ b/drivers/cxl/core/trace.h
>@@ -539,7 +539,6 @@ TRACE_EVENT(cxl_dram,
> __field(u64, dpa)
> __field(u8, descriptor)
> __field(u8, type)
>- __field(u8, sub_type)
> __field(u8, transaction_type)
> __field(u8, channel)
> __field(u16, validity_flags) @@ -553,11 +552,13 @@
>TRACE_EVENT(cxl_dram,
> __field(u8, bank_group) /* Out of order to pack trace record */
> __field(u8, bank) /* Out of order to pack trace record */
> __field(u8, dpa_flags) /* Out of order to pack trace record */
>- __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
>+ /* The following are out of order to pack the trace
>+ record */
> __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
>+ __field(u32, cvme_count)
>+ __field(u8, sub_type)
> __field(u8, sub_channel)
> __field(u8, cme_threshold_ev_flags)
>- __field(u32, cvme_count)
>+ __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
> ),
>
> TP_fast_assign(
>
>
>
>Other than that it looks good. Perhaps Dave can just squash this hunk?
>
>Ira
>
>[snip]
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1
2025-01-10 20:18 ` Dave Jiang
@ 2025-01-11 9:22 ` Shiju Jose
0 siblings, 0 replies; 19+ messages in thread
From: Shiju Jose @ 2025-01-11 9:22 UTC (permalink / raw)
To: Dave Jiang, Jonathan Cameron
Cc: dan.j.williams@intel.com, alison.schofield@intel.com,
nifan.cxl@gmail.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, dave@stgolabs.net, linux-cxl@vger.kernel.org,
linux-kernel@vger.kernel.org, Linuxarm, tanxiaofei, Zengtao (B)
>-----Original Message-----
>From: Dave Jiang <dave.jiang@intel.com>
>Sent: 10 January 2025 20:18
>To: Shiju Jose <shiju.jose@huawei.com>; Jonathan Cameron
><jonathan.cameron@huawei.com>
>Cc: dan.j.williams@intel.com; alison.schofield@intel.com; nifan.cxl@gmail.com;
>vishal.l.verma@intel.com; ira.weiny@intel.com; dave@stgolabs.net; linux-
>cxl@vger.kernel.org; linux-kernel@vger.kernel.org; Linuxarm
><linuxarm@huawei.com>; tanxiaofei <tanxiaofei@huawei.com>; Zengtao (B)
><prime.zeng@hisilicon.com>
>Subject: Re: [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1
>
>
>
>On 1/10/25 9:46 AM, Shiju Jose wrote:
>>> -----Original Message-----
>>> From: Jonathan Cameron <jonathan.cameron@huawei.com>
>>> Sent: 10 January 2025 16:07
>>> To: Shiju Jose <shiju.jose@huawei.com>
>>> Cc: dave.jiang@intel.com; dan.j.williams@intel.com;
>>> alison.schofield@intel.com; nifan.cxl@gmail.com;
>>> vishal.l.verma@intel.com; ira.weiny@intel.com; dave@stgolabs.net;
>>> linux-cxl@vger.kernel.org; linux-kernel@vger.kernel.org; Linuxarm
>>> <linuxarm@huawei.com>; tanxiaofei <tanxiaofei@huawei.com>; Zengtao
>>> (B) <prime.zeng@hisilicon.com>
>>> Subject: Re: [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1
>>>
>>> On Fri, 10 Jan 2025 11:55:50 +0000
>>> <shiju.jose@huawei.com> wrote:
>>>
>>>> From: Shiju Jose <shiju.jose@huawei.com>
>>>>
>>>> Add updates in the CXL events records and CXL trace events
>>>> implementations for the changes in CXL spec rev 3.1.
>>>>
>>>> Shiju Jose (6):
>>>> cxl/events: Update Common Event Record to CXL spec rev 3.1
>>>> cxl/events: Add Component Identifier formatting for CXL spec rev 3.1
>>>> cxl/events: Update General Media Event Record to CXL spec rev 3.1
>>>> cxl/events: Update DRAM Event Record to CXL spec rev 3.1
>>>> cxl/events: Update Memory Module Event Record to CXL spec rev 3.1
>>>> cxl/test: Update test code for event records to CXL spec rev 3.1
>>>>
>>>> Changes:
>>>> V4 -> V5
>>>> 1. Reverted changes made in v4 for overcoming parsing error when
>>>> libtraceevent in userspace parses the CXL trace events, for rasdaemon.
>>>> This was due to trace event's format file is larger than PAGE_SIZE,
>>>> not supported reading complete format file in one go in the kernel
>>>> and thus fixed in the rasdaemon.
>>>
>>> Great to see that resolved.
>>>
>>>> 2. Rebased to v6.13-rc5.
>>>
>>> Should probably say why when doing a rebase to something other than rc1.
>>> In this case this is what cxl.git/next is based on after some fixes
>>> earlier in the cycle so a sensible choice for this set.
>>
>> I checked. These patches applied cleanly in cxl.git/next and buid okay.
>
>Hi Shiju,
>Can you please apply Ira's suggestions and respin a v6? Thanks!
Hi Dave,
Sure. I added Ira's suggestions and please find v6 of the series here.
https://lore.kernel.org/all/20250111091756.1682-1-shiju.jose@huawei.com/
Thanks,
Shiju
>
[...]
>
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2025-01-11 9:23 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
2025-01-10 11:55 ` [PATCH v5 1/6] cxl/events: Update Common Event Record " shiju.jose
2025-01-10 17:35 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 2/6] cxl/events: Add Component Identifier formatting for " shiju.jose
2025-01-10 17:43 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 3/6] cxl/events: Update General Media Event Record to " shiju.jose
2025-01-10 17:54 ` Ira Weiny
2025-01-10 18:30 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 4/6] cxl/events: Update DRAM " shiju.jose
2025-01-10 18:27 ` Ira Weiny
2025-01-11 9:16 ` Shiju Jose
2025-01-10 11:55 ` [PATCH v5 5/6] cxl/events: Update Memory Module " shiju.jose
2025-01-10 18:46 ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 6/6] cxl/test: Update test code for event records " shiju.jose
2025-01-10 18:48 ` Ira Weiny
2025-01-10 16:06 ` [PATCH v5 0/6] Update Event Records " Jonathan Cameron
2025-01-10 16:46 ` Shiju Jose
2025-01-10 20:18 ` Dave Jiang
2025-01-11 9:22 ` Shiju Jose
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox