* [PATCH 1/6] arm64: dts: rockchip: fix rk3576 pcie unit addresses
2025-05-18 22:04 [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
@ 2025-05-18 22:04 ` Heiko Stuebner
2025-05-18 22:04 ` [PATCH 2/6] arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node Heiko Stuebner
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-05-18 22:04 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ziyao, kever.yang, nicolas.frattaroli,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
kernel test robot
The rk3576 pcie nodes currently use the apb register as their unit address
which is the second reg area defined in the binding.
As can be seen by the dtc warnings like
../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1346.24-1398.5: Warning (simple_bus_reg): /soc/pcie@2a200000: simple-bus unit address format error, expected "22000000"
../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1400.24-1452.5: Warning (simple_bus_reg): /soc/pcie@2a210000: simple-bus unit address format error, expected "22400000"
using the first reg area as the unit address seems to be preferred.
This is the dbi area per the binding, so adapt the unit address accordingly
and move the nodes to their new position.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 216 +++++++++++------------
1 file changed, 108 insertions(+), 108 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 79800959b797..3b62e037772a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -466,6 +466,114 @@ soc {
#size-cells = <2>;
ranges;
+ pcie0: pcie@22000000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ reg = <0x0 0x22000000 0x0 0x00400000>,
+ <0x0 0x2a200000 0x0 0x00010000>,
+ <0x0 0x20000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x0 0xf>;
+ clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
+ <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
+ <&cru CLK_PCIE0_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_PHP>;
+ ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
+ 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
+ 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie0_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie1: pcie@22400000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ reg = <0x0 0x22400000 0x0 0x00400000>,
+ <0x0 0x2a210000 0x0 0x00010000>,
+ <0x0 0x21000000 0x0 0x00100000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x20 0x2f>;
+ clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
+ <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
+ <&cru CLK_PCIE1_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
+ phys = <&combphy1_psu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_SUBPHP>;
+ ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
+ 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
+ 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ reset-names = "pwr", "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
usb_drd0_dwc3: usb@23000000 {
compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
reg = <0x0 0x23000000 0x0 0x400000>;
@@ -1343,114 +1451,6 @@ qos_npu_m1ro: qos@27f22100 {
reg = <0x0 0x27f22100 0x0 0x20>;
};
- pcie0: pcie@2a200000 {
- compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
- reg = <0x0 0x22000000 0x0 0x00400000>,
- <0x0 0x2a200000 0x0 0x00010000>,
- <0x0 0x20000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- bus-range = <0x0 0xf>;
- clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
- <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
- <&cru CLK_PCIE0_AUX>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux";
- device_type = "pci";
- interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie0_intc 0>,
- <0 0 0 2 &pcie0_intc 1>,
- <0 0 0 3 &pcie0_intc 2>,
- <0 0 0 4 &pcie0_intc 3>;
- linux,pci-domain = <0>;
- max-link-speed = <2>;
- num-ib-windows = <8>;
- num-viewport = <8>;
- num-ob-windows = <2>;
- num-lanes = <1>;
- phys = <&combphy0_ps PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3576_PD_PHP>;
- ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
- 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
- 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
- reset-names = "pwr", "pipe";
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie0_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- pcie1: pcie@2a210000 {
- compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
- reg = <0x0 0x22400000 0x0 0x00400000>,
- <0x0 0x2a210000 0x0 0x00010000>,
- <0x0 0x21000000 0x0 0x00100000>;
- reg-names = "dbi", "apb", "config";
- bus-range = <0x20 0x2f>;
- clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
- <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
- <&cru CLK_PCIE1_AUX>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk",
- "aux";
- device_type = "pci";
- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie1_intc 0>,
- <0 0 0 2 &pcie1_intc 1>,
- <0 0 0 3 &pcie1_intc 2>,
- <0 0 0 4 &pcie1_intc 3>;
- linux,pci-domain = <0>;
- max-link-speed = <2>;
- num-ib-windows = <8>;
- num-viewport = <8>;
- num-ob-windows = <2>;
- num-lanes = <1>;
- phys = <&combphy1_psu PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power RK3576_PD_SUBPHP>;
- ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
- 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
- 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
- reset-names = "pwr", "pipe";
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie1_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
gmac0: ethernet@2a220000 {
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
reg = <0x0 0x2a220000 0x0 0x10000>;
--
2.47.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/6] arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
2025-05-18 22:04 [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
2025-05-18 22:04 ` [PATCH 1/6] arm64: dts: rockchip: fix rk3576 pcie unit addresses Heiko Stuebner
@ 2025-05-18 22:04 ` Heiko Stuebner
2025-05-18 22:04 ` [PATCH 3/6] arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi Heiko Stuebner
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-05-18 22:04 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ziyao, kever.yang, nicolas.frattaroli,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
kernel test robot
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
as dtc points out:
../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
Move the pinctrl node outside and adapt the indentation.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 136 +++++++++++------------
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 3b62e037772a..0e0a37849874 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -429,6 +429,74 @@ simple-audio-card,cpu {
};
};
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3576-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@27320000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x27320000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2ae10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2ae20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2ae30000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae30000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@2ae40000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae40000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+ };
+
pmu_a53: pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -2347,74 +2415,6 @@ scmi_shmem: scmi-shmem@4010f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x4010f000 0x0 0x100>;
};
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3576-pinctrl";
- rockchip,grf = <&ioc_grf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@27320000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x27320000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@2ae10000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae10000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 32 32>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@2ae20000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae20000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 64 32>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@2ae30000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae30000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 96 32>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@2ae40000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0x2ae40000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 128 32>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
- };
};
};
--
2.47.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/6] arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
2025-05-18 22:04 [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
2025-05-18 22:04 ` [PATCH 1/6] arm64: dts: rockchip: fix rk3576 pcie unit addresses Heiko Stuebner
2025-05-18 22:04 ` [PATCH 2/6] arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node Heiko Stuebner
@ 2025-05-18 22:04 ` Heiko Stuebner
2025-05-18 22:04 ` [PATCH 4/6] arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node Heiko Stuebner
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-05-18 22:04 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ziyao, kever.yang, nicolas.frattaroli,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
Two empty lines between nodes, is one too many.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 0e0a37849874..b6e946e68b09 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -2000,7 +2000,6 @@ i2c5: i2c@2ac80000 {
status = "disabled";
};
-
i2c6: i2c@2ac90000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ac90000 0x0 0x1000>;
--
2.47.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/6] arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
2025-05-18 22:04 [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
` (2 preceding siblings ...)
2025-05-18 22:04 ` [PATCH 3/6] arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi Heiko Stuebner
@ 2025-05-18 22:04 ` Heiko Stuebner
2025-05-18 22:04 ` [PATCH 5/6] arm64: dts: rockchip: fix rk3562 pcie unit addresses Heiko Stuebner
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-05-18 22:04 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ziyao, kever.yang, nicolas.frattaroli,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
as dtc points out:
../arch/arm64/boot/dts/rockchip/rk3528.dtsi:870.20-936.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
Move the pinctrl node outside and adapt the indentation.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 136 +++++++++++------------
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index b2724c969a76..d1c72b52aa4e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -95,6 +95,74 @@ scmi_clk: protocol@14 {
};
};
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff610000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff610000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ffaf0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffaf0000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ffb00000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb00000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffb10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffb20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -866,74 +934,6 @@ dmac: dma-controller@ffd60000 {
#dma-cells = <1>;
arm,pl330-periph-burst;
};
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3528-pinctrl";
- rockchip,grf = <&ioc_grf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@ff610000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff610000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 0 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@ffaf0000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffaf0000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 32 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@ffb00000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffb00000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 64 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@ffb10000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffb10000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 96 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@ffb20000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffb20000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 128 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
};
};
--
2.47.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 5/6] arm64: dts: rockchip: fix rk3562 pcie unit addresses
2025-05-18 22:04 [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
` (3 preceding siblings ...)
2025-05-18 22:04 ` [PATCH 4/6] arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node Heiko Stuebner
@ 2025-05-18 22:04 ` Heiko Stuebner
2025-05-18 22:04 ` [PATCH 6/6] arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node Heiko Stuebner
2025-05-20 19:09 ` [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
6 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-05-18 22:04 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ziyao, kever.yang, nicolas.frattaroli,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
The rk3562 pcie node currently uses the apb register as its unit address
which is the second reg area defined in the binding.
As can be seen by the dtc warnings like
../arch/arm64/boot/dts/rockchip/rk3562.dtsi:624.26-675.5: Warning (simple_bus_reg): /soc/pcie@ff500000: simple-bus unit address format error, expected "fe000000"
using the first reg area as the unit address seems to be preferred.
This is the dbi area per the binding, so adapt the unit address accordingly
and move the nodes to their new position.
With the move also move the reg + reg-names below the compatible, as is the
preferred position.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3562.dtsi | 106 +++++++++++------------
1 file changed, 53 insertions(+), 53 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
index 6268f84efa13..292e82ec5d45 100644
--- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
@@ -249,6 +249,59 @@ soc {
#size-cells = <2>;
ranges;
+ pcie2x1: pcie@fe000000 {
+ compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie";
+ reg = <0x0 0xfe000000 0x0 0x400000>,
+ <0x0 0xff500000 0x0 0x10000>,
+ <0x0 0xfc000000 0x0 0x100000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x0 0xff>;
+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
+ <&cru CLK_PCIE20_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
+ <0 0 0 2 &pcie2x1_intc 1>,
+ <0 0 0 3 &pcie2x1_intc 2>,
+ <0 0 0 4 &pcie2x1_intc 3>;
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ num-lanes = <1>;
+ phys = <&combphy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power 15>;
+ ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
+ 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
+ 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
+ resets = <&cru SRST_PCIE20_POWERUP>;
+ reset-names = "pipe";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie2x1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
gic: interrupt-controller@fe901000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -621,59 +674,6 @@ gpu: gpu@ff320000 {
status = "disabled";
};
- pcie2x1: pcie@ff500000 {
- compatible = "rockchip,rk3562-pcie", "rockchip,rk3568-pcie";
- bus-range = <0x0 0xff>;
- clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
- <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
- <&cru CLK_PCIE20_AUX>;
- clock-names = "aclk_mst", "aclk_slv",
- "aclk_dbi", "pclk", "aux";
- device_type = "pci";
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
- <0 0 0 2 &pcie2x1_intc 1>,
- <0 0 0 3 &pcie2x1_intc 2>,
- <0 0 0 4 &pcie2x1_intc 3>;
- linux,pci-domain = <0>;
- max-link-speed = <2>;
- num-ib-windows = <8>;
- num-viewport = <8>;
- num-ob-windows = <2>;
- num-lanes = <1>;
- phys = <&combphy PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- power-domains = <&power 15>;
- ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
- 0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
- 0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
- reg = <0x0 0xfe000000 0x0 0x400000>,
- <0x0 0xff500000 0x0 0x10000>,
- <0x0 0xfc000000 0x0 0x100000>;
- reg-names = "dbi", "apb", "config";
- resets = <&cru SRST_PCIE20_POWERUP>;
- reset-names = "pipe";
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie2x1_intc: legacy-interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
spi1: spi@ff640000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xff640000 0x0 0x1000>;
--
2.47.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 6/6] arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
2025-05-18 22:04 [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
` (4 preceding siblings ...)
2025-05-18 22:04 ` [PATCH 5/6] arm64: dts: rockchip: fix rk3562 pcie unit addresses Heiko Stuebner
@ 2025-05-18 22:04 ` Heiko Stuebner
2025-05-20 19:09 ` [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
6 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-05-18 22:04 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, ziyao, kever.yang, nicolas.frattaroli,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
as dtc points out:
../arch/arm64/boot/dts/rockchip/rk3562.dtsi:1115.20-1181.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
Move the pinctrl node outside and adapt the indentation.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3562.dtsi | 136 +++++++++++------------
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
index 292e82ec5d45..def504ffa326 100644
--- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
@@ -218,6 +218,74 @@ scmi_clk: protocol@14 {
};
};
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3562-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff260000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff260000 0x0 0x100>;
+ clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ff620000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff620000 0x0 0x100>;
+ clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ff630000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff630000 0x0 0x100>;
+ clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffac0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffac0000 0x0 0x100>;
+ clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffad0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffad0000 0x0 0x100>;
+ clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -1111,74 +1179,6 @@ saradc1: adc@ffaa0000 {
#io-channel-cells = <1>;
status = "disabled";
};
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3562-pinctrl";
- rockchip,grf = <&ioc_grf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@ff260000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff260000 0x0 0x100>;
- clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@ff620000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff620000 0x0 0x100>;
- clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 32 32>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@ff630000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff630000 0x0 0x100>;
- clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 64 32>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@ffac0000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffac0000 0x0 0x100>;
- clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 96 32>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@ffad0000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffad0000 0x0 0x100>;
- clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
- gpio-controller;
- gpio-ranges = <&pinctrl 0 128 32>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- };
- };
};
};
--
2.47.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576
2025-05-18 22:04 [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
` (5 preceding siblings ...)
2025-05-18 22:04 ` [PATCH 6/6] arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node Heiko Stuebner
@ 2025-05-20 19:09 ` Heiko Stuebner
6 siblings, 0 replies; 8+ messages in thread
From: Heiko Stuebner @ 2025-05-20 19:09 UTC (permalink / raw)
To: Heiko Stuebner
Cc: robh, krzk+dt, conor+dt, ziyao, kever.yang, nicolas.frattaroli,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
On Mon, 19 May 2025 00:04:42 +0200, Heiko Stuebner wrote:
> Inspired by the issue reported by the kernel-test-robot in
> http://lore.kernel.org/r/202505150745.PQT9TLYX-lkp@intel.com
>
> fix it and similar issues in all of rk3528, rk3562 and rk3576.
>
>
> Heiko Stuebner (6):
> arm64: dts: rockchip: fix rk3576 pcie unit addresses
> arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
> arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
> arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
> arm64: dts: rockchip: fix rk3562 pcie unit addresses
> arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
>
> [...]
Applied, thanks!
[1/6] arm64: dts: rockchip: fix rk3576 pcie unit addresses
commit: 4d2587e0e1ce7145a38802fa281f4f1f411ec56f
[2/6] arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
commit: 8ff721f60257d550daf524fc559c0f0d2176b198
[3/6] arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
commit: f8b11d8cfbfc8a0232c1e7cc6af10583c8bdb3f1
[4/6] arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
commit: 7d086f78fe09fb94eb3b2e12436f2feed21d9c1e
[5/6] arm64: dts: rockchip: fix rk3562 pcie unit addresses
commit: 25d3e1d2558caf823902e3b1b83901f5ac65af8d
[6/6] arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
commit: dfab90b9580c2fbc4e8bb4ceee97cdd75832a6e7
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 8+ messages in thread