From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: <linux-kernel@vger.kernel.org>, <iommu@lists.linux.dev>,
<joro@8bytes.org>, <jgg@nvidia.com>
Cc: <yi.l.liu@intel.com>, <kevin.tian@intel.com>,
<nicolinc@nvidia.com>, <vasant.hegde@amd.com>,
<jon.grimm@amd.com>, <santosh.shukla@amd.com>,
<sairaj.arunkodilkar@amd.com>, <jay.chen@amd.com>,
<wvw@google.com>, <wnliu@google.com>, <dantuluris@google.com>,
<chriscli@google.com>, <kpsingh@google.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: [PATCH v3 18/22] iommu/amd: Introduce helper function for updating device ID mapping table
Date: Mon, 29 Jun 2026 15:35:31 +0000 [thread overview]
Message-ID: <20260629153535.15775-19-suravee.suthikulpanit@amd.com> (raw)
In-Reply-To: <20260629153535.15775-1-suravee.suthikulpanit@amd.com>
AMD vIOMMU hardware uses the Device ID mapping table to map Guest Device ID
(GDevID) to Host Device ID when it virtualises guest IOMMU commands.
It uses GID and GDevID to indexe into the table to look up host device ID.
Linux IOMMU driver programs the table entry using VFCntlMMIO Guest Device
Map Control Register.
Introduce amd_viommu_set/clear_device_mapping(), which are used to set
the entry when initialize the IOMMUFD vDevice. Clearing the entry is
done during VM destroy.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd/amd_viommu.h | 8 ++++++
drivers/iommu/amd/iommufd.c | 3 ++
drivers/iommu/amd/viommu.c | 52 ++++++++++++++++++++++++++++++++++
3 files changed, 63 insertions(+)
diff --git a/drivers/iommu/amd/amd_viommu.h b/drivers/iommu/amd/amd_viommu.h
index b6fd5ffc3b82..3a8f41baaab9 100644
--- a/drivers/iommu/amd/amd_viommu.h
+++ b/drivers/iommu/amd/amd_viommu.h
@@ -20,6 +20,9 @@ void amd_viommu_uninit_one(struct amd_iommu *iommu, struct amd_iommu_viommu *vio
int amd_viommu_domain_id_update(struct amd_iommu *iommu, u16 gid,
u16 hdom_id, u16 gdom_id);
+
+void amd_viommu_set_device_mapping(struct amd_iommu *iommu, u16 hDevId,
+ u16 guestId, u16 gDevId);
#else
static inline int amd_viommu_init(struct amd_iommu *iommu)
@@ -45,6 +48,11 @@ static inline void amd_viommu_uninit_one(struct amd_iommu *iommu, struct amd_iom
{
}
+static inline void amd_viommu_set_device_mapping(struct amd_iommu *iommu, u16 hDevId,
+ u16 guestId, u16 gDevId)
+{
+}
+
#endif /* CONFIG_AMD_IOMMU_IOMMUFD */
#endif /* AMD_VIOMMU_H */
diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c
index 1d159b78e37c..8b569b469a07 100644
--- a/drivers/iommu/amd/iommufd.c
+++ b/drivers/iommu/amd/iommufd.c
@@ -136,6 +136,7 @@ static int _amd_viommu_vdevice_init(struct iommufd_vdevice *vdev)
struct pci_dev *pdev = to_pci_dev(vdev->idev->dev);
struct iommufd_viommu *viommu = vdev->viommu;
struct amd_iommu_viommu *aviommu = container_of(viommu, struct amd_iommu_viommu, core);
+ struct amd_iommu *iommu = container_of(viommu->iommu_dev, struct amd_iommu, iommu);
if (!pdev) {
pr_err("%s: not a PCI device\n", __func__);
@@ -154,6 +155,8 @@ static int _amd_viommu_vdevice_init(struct iommufd_vdevice *vdev)
pr_debug("%s: gid=%#x, hdev_id=%#x, gdev_id=%#x\n", __func__,
dev_data->gid, pci_dev_id(pdev), dev_data->gDevId);
+ amd_viommu_set_device_mapping(iommu, pci_dev_id(pdev), dev_data->gid, dev_data->gDevId);
+
return 0;
}
diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c
index 9b471aadd5df..7b3127d829c5 100644
--- a/drivers/iommu/amd/viommu.c
+++ b/drivers/iommu/amd/viommu.c
@@ -40,6 +40,7 @@
#define VIOMMU_DOMID_MAPPING_BASE 0x2000000000ULL
#define VIOMMU_DOMID_MAPPING_ENTRY_SIZE (1 << 19)
+#define VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET 0x00
#define VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL1_OFFSET 0x08
LIST_HEAD(viommu_devid_map);
@@ -429,6 +430,53 @@ static void __maybe_unused free_private_vm_region(struct amd_iommu *iommu, u64 *
*entry = NULL;
}
+#define DEVID_ENTRY_GDEVID_MASK GENMASK_ULL(61, 46)
+#define DEVID_ENTRY_HDEVID_MASK GENMASK_ULL(29, 14)
+#define DEVID_ENTRY_WRITE BIT_ULL(63)
+#define DEVID_ENTRY_VALID BIT_ULL(0)
+
+/*
+ * Program the DevID via VFCTRL registers
+ * This function will be called during VM init via VFIO.
+ */
+void amd_viommu_set_device_mapping(struct amd_iommu *iommu, u16 hDevId,
+ u16 guestId, u16 gDevId)
+{
+ u64 val;
+ u8 __iomem *vfctrl;
+
+ pr_debug("%s: iommu_devid=%#x, gid=%#x, hDevId=%#x, gDevId=%#x\n",
+ __func__, pci_dev_id(iommu->dev), guestId, hDevId, gDevId);
+
+ val = FIELD_PREP(DEVID_ENTRY_GDEVID_MASK, gDevId) |
+ FIELD_PREP(DEVID_ENTRY_HDEVID_MASK, hDevId) |
+ DEVID_ENTRY_WRITE | DEVID_ENTRY_VALID;
+
+ vfctrl = VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId);
+
+ writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET);
+}
+
+/*
+ * Clear the DevID via VFCTRL registers
+ * This function will be called during VM destroy via VFIO.
+ */
+static void clear_device_mapping(struct amd_iommu *iommu, u16 guestId, u16 gDevId)
+{
+ u64 val;
+ u8 __iomem *vfctrl;
+
+ /*
+ * Clear the DevID in VFCTRL registers
+ */
+ val = FIELD_PREP(DEVID_ENTRY_GDEVID_MASK, gDevId) |
+ FIELD_PREP(DEVID_ENTRY_HDEVID_MASK, 0) |
+ DEVID_ENTRY_WRITE | DEVID_ENTRY_VALID;
+
+ vfctrl = VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId);
+ writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET);
+}
+
static void viommu_clear_mapping(struct amd_iommu *iommu,
struct amd_iommu_viommu *aviommu)
{
@@ -443,6 +491,10 @@ static void viommu_clear_mapping(struct amd_iommu *iommu,
*/
for (i = 0; i <= VIOMMU_MAX_GDOMID; i++)
amd_viommu_domain_id_update(iommu, gid, aviommu->parent->id, i);
+
+ for (i = 0; i <= VIOMMU_MAX_GDEVID; i++)
+ clear_device_mapping(iommu, gid, i);
+
}
void amd_viommu_uninit_one(struct amd_iommu *iommu, struct amd_iommu_viommu *aviommu)
--
2.34.1
next prev parent reply other threads:[~2026-06-29 15:42 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-29 15:35 [PATCH v3 00/22] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 01/22] iommu/amd: Make amd_iommu_completion_wait() non-static Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 02/22] iommu/amd: Introduce vIOMMU-specific events and event Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 03/22] iommu/amd: Detect and initialize AMD vIOMMU feature Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 04/22] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 05/22] iommu/amd: Allocate Guest IDs for IOMMUFD vIOMMU instances Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 06/22] iommu/amd: Map vIOMMU VF and VF Control MMIO BARs Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 07/22] iommu/amd: Add support for AMD vIOMMU VF MMIO region Suravee Suthikulpanit
2026-07-07 14:33 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 08/22] iommu/amd: Introduce Reset vMMIO Command Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 09/22] iommu/amd: Introduce and map vIOMMU private IPA region Suravee Suthikulpanit
2026-07-07 14:07 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 10/22] iommu/amd: Pass iommu to device_flush_dte() Suravee Suthikulpanit
2026-07-07 14:18 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 11/22] iommu/amd: Export amd_iommu_alloc_dev_data() helper Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 12/22] iommu/amd: Pass iommu and devid to amd_iommu_make_clear_dte() Suravee Suthikulpanit
2026-07-07 14:20 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 13/22] iommu/amd: Assign IOMMU Private Address domain to IOMMU Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 14/22] iommu/amd: Add per-VM private IPA alloc/map helpers Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 15/22] iommu/amd: Add helper functions to manage DevID / DomID mapping tables Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 16/22] iommu/amd: Introduce IOMMUFD vDevice support for AMD Suravee Suthikulpanit
2026-07-07 14:31 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 17/22] iommu/amd: Introduce helper function for updating domain ID mapping table Suravee Suthikulpanit
2026-07-07 14:32 ` Jason Gunthorpe
2026-06-29 15:35 ` Suravee Suthikulpanit [this message]
2026-06-29 15:35 ` [PATCH v3 19/22] iommu/amd: Add per-segment translate device ID pool Suravee Suthikulpanit
2026-07-07 14:36 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 20/22] iommu/amd: Reserve translate-device-id for PCI requestor aliases Suravee Suthikulpanit
2026-07-07 14:39 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 21/22] iommu/amd: Add translation DTE and VFctrl TransDevID helpers Suravee Suthikulpanit
2026-07-07 14:43 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 22/22] iommu/amd: Assign per-vIOMMU translate device ID Suravee Suthikulpanit
2026-07-07 14:45 ` [PATCH v3 00/22] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Jason Gunthorpe
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