From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: <linux-kernel@vger.kernel.org>, <iommu@lists.linux.dev>,
<joro@8bytes.org>, <jgg@nvidia.com>
Cc: <yi.l.liu@intel.com>, <kevin.tian@intel.com>,
<nicolinc@nvidia.com>, <vasant.hegde@amd.com>,
<jon.grimm@amd.com>, <santosh.shukla@amd.com>,
<sairaj.arunkodilkar@amd.com>, <jay.chen@amd.com>,
<wvw@google.com>, <wnliu@google.com>, <dantuluris@google.com>,
<chriscli@google.com>, <kpsingh@google.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: [PATCH v3 19/22] iommu/amd: Add per-segment translate device ID pool
Date: Mon, 29 Jun 2026 15:35:32 +0000 [thread overview]
Message-ID: <20260629153535.15775-20-suravee.suthikulpanit@amd.com> (raw)
In-Reply-To: <20260629153535.15775-1-suravee.suthikulpanit@amd.com>
Track translate-device-id slots per PCI segment so real PCI device IDs can
be reserved for normal DTE programming and excluded from dynamic allocation
for vIOMMU translation DTEs.
Add amd_iommu_pci_seg_trans_devid_init/fini() during segment setup and
teardown, amd_iommu_trans_devid_reserve() for attach-time reservation, and
trans_devid.c implementing the xarray-backed state machine.
Call the reserve hook from amd_iommu_attach_device() before programming
the DTE.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd/Makefile | 2 +-
drivers/iommu/amd/amd_iommu.h | 19 +++++++
drivers/iommu/amd/amd_iommu_types.h | 17 ++++++
drivers/iommu/amd/init.c | 3 ++
drivers/iommu/amd/iommu.c | 12 +++++
drivers/iommu/amd/trans_devid.c | 83 +++++++++++++++++++++++++++++
6 files changed, 135 insertions(+), 1 deletion(-)
create mode 100644 drivers/iommu/amd/trans_devid.c
diff --git a/drivers/iommu/amd/Makefile b/drivers/iommu/amd/Makefile
index e1e824b9c7b0..12c3fe83e4ce 100644
--- a/drivers/iommu/amd/Makefile
+++ b/drivers/iommu/amd/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += iommu.o init.o quirks.o ppr.o pasid.o
-obj-$(CONFIG_AMD_IOMMU_IOMMUFD) += iommufd.o nested.o viommu.o
+obj-$(CONFIG_AMD_IOMMU_IOMMUFD) += iommufd.o nested.o viommu.o trans_devid.o
obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += debugfs.o
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index aaa57840e904..f99225be5d07 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -218,6 +218,25 @@ void amd_iommu_update_dte(struct amd_iommu *iommu,
struct dev_table_entry *new);
int amd_iommu_completion_wait(struct amd_iommu *iommu);
+/* Per-segment translate-device-id pool (CONFIG_AMD_IOMMU_IOMMUFD) */
+#ifdef CONFIG_AMD_IOMMU_IOMMUFD
+void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg);
+void amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg);
+int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id);
+#else
+static inline void
+amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg) { }
+static inline void
+amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg) { }
+#endif
+
+int amd_iommu_set_translate_dte(struct amd_iommu *iommu,
+ struct protection_domain *pdom,
+ u16 gid, u32 trans_devid);
+void amd_iommu_clear_translate_dte(struct amd_iommu *iommu, u32 trans_devid);
+void amd_iommu_update_vfctrl_mmio_translate_devid(struct amd_iommu *iommu,
+ u16 gid, u32 trans_devid);
+
static inline void
amd_iommu_make_clear_dte(struct amd_iommu *iommu, u16 devid,
struct dev_table_entry *new)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 027d9cfa5533..91cdb61b5254 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -612,6 +612,14 @@ PT_IOMMU_CHECK_DOMAIN(struct protection_domain, iommu, domain);
PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv1.iommu, domain);
PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv2.iommu, domain);
+#ifdef CONFIG_AMD_IOMMU_IOMMUFD
+enum trans_devid_state {
+ TRANS_DEVID_FREE = 0,
+ TRANS_DEVID_RESERVED,
+ TRANS_DEVID_ALLOCATED,
+};
+#endif
+
/*
* This structure contains information about one PCI segment in the system.
*/
@@ -673,6 +681,15 @@ struct amd_iommu_pci_seg {
* parsing time.
*/
struct list_head unity_map;
+
+#ifdef CONFIG_AMD_IOMMU_IOMMUFD
+ /*
+ * Per-segment translate-device-id allocation. The xarray is indexed by
+ * the translate-device-id. The value is the state (enum trans_devid_state).
+ */
+ struct mutex trans_devid_mutex;
+ struct xarray trans_devid_xa;
+#endif
};
/*
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 6e69b3dd8b1e..622bc0337eda 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -1737,6 +1737,8 @@ static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id,
if (alloc_rlookup_table(pci_seg))
goto err_free_alias_table;
+ amd_iommu_pci_seg_trans_devid_init(pci_seg);
+
return pci_seg;
err_free_alias_table:
@@ -1768,6 +1770,7 @@ static void __init free_pci_segments(void)
for_each_pci_segment_safe(pci_seg, next) {
list_del(&pci_seg->list);
+ amd_iommu_pci_seg_trans_devid_fini(pci_seg);
free_irq_lookup_table(pci_seg);
free_rlookup_table(pci_seg);
free_alias_table(pci_seg);
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 3b59938c2f86..01b755a2baed 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -3075,6 +3075,18 @@ static int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev,
if (dom->dirty_ops && !amd_iommu_hd_support(iommu))
return -EINVAL;
+#if IS_ENABLED(CONFIG_AMD_IOMMU_IOMMUFD)
+ /* Translate-device-id reservation must be done before setting up
+ * the DTE for the device to make sure that the id has not been allocated
+ * yet. (See amd_iommu_trans_devid_alloc().)
+ */
+ ret = amd_iommu_trans_devid_reserve(iommu->pci_seg, dev_data->devid);
+ if (ret) {
+ pr_err("%s: Failed to reserve device id %#x\n", __func__, dev_data->devid);
+ return ret;
+ }
+#endif
+
if (dev_data->domain)
detach_device(dev);
diff --git a/drivers/iommu/amd/trans_devid.c b/drivers/iommu/amd/trans_devid.c
new file mode 100644
index 000000000000..e5cca409d134
--- /dev/null
+++ b/drivers/iommu/amd/trans_devid.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Advanced Micro Devices, Inc.
+ *
+ * AMD vIOMMU translate-device-id management.
+ *
+ * The id must be allocated from unused range. It is used to program the vIOMMU VF Control
+ * register to specify the DTE used to contain the GPA->SPA mapping (v1 page table).
+ */
+
+#include <linux/kernel.h>
+#include <linux/xarray.h>
+
+#include "amd_iommu.h"
+
+static inline enum trans_devid_state trans_devid_xa_get_state(void *entry)
+{
+ if (!entry)
+ return TRANS_DEVID_FREE;
+ if (WARN_ON_ONCE(!xa_is_value(entry)))
+ return TRANS_DEVID_FREE;
+ return (enum trans_devid_state)xa_to_value(entry);
+}
+
+static inline void *trans_devid_xa_mk_state(enum trans_devid_state s)
+{
+ return xa_mk_value((unsigned long)s);
+}
+
+void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg)
+{
+ mutex_init(&pci_seg->trans_devid_mutex);
+ xa_init(&pci_seg->trans_devid_xa);
+}
+
+void amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg)
+{
+ xa_destroy(&pci_seg->trans_devid_xa);
+}
+
+/**
+ * amd_iommu_trans_devid_reserve - occupy @id so it is never returned by alloc
+ *
+ * Reservation is done when attaching device to a domain (see amd_iommu_attach_device()).
+ *
+ * Note: Since PCI hot-plug devices are enumerated during runtime, they could clash
+ * with the translate-device-id allocation. In such case, amd_iommu_trans_devid_reserve()
+ * could fail with %-EBUSY. This can be avoided by reserving the hot-plug id range if it
+ * is known in advance.
+ *
+ * Return: 0 on success, %-EBUSY if @id is already allocated. A second reserve of
+ * an already-reserved @id succeeds.
+ */
+int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id)
+{
+ void *entry, *old;
+ int ret = 0;
+
+ mutex_lock(&pci_seg->trans_devid_mutex);
+ entry = xa_load(&pci_seg->trans_devid_xa, id);
+ switch (trans_devid_xa_get_state(entry)) {
+ case TRANS_DEVID_ALLOCATED:
+ ret = -EBUSY;
+ break;
+ case TRANS_DEVID_RESERVED:
+ break;
+ case TRANS_DEVID_FREE:
+ old = xa_store(&pci_seg->trans_devid_xa, id,
+ trans_devid_xa_mk_state(TRANS_DEVID_RESERVED), GFP_KERNEL);
+ if (xa_is_err(old)) {
+ ret = xa_err(old);
+ break;
+ }
+ WARN_ON_ONCE(old);
+ break;
+ }
+ mutex_unlock(&pci_seg->trans_devid_mutex);
+
+ if (!ret)
+ pr_debug("%s: Reserved trans_devid %#x (seg %#x)\n", __func__, id,
+ pci_seg->id);
+ return ret;
+}
--
2.34.1
next prev parent reply other threads:[~2026-06-29 15:42 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-29 15:35 [PATCH v3 00/22] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 01/22] iommu/amd: Make amd_iommu_completion_wait() non-static Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 02/22] iommu/amd: Introduce vIOMMU-specific events and event Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 03/22] iommu/amd: Detect and initialize AMD vIOMMU feature Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 04/22] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 05/22] iommu/amd: Allocate Guest IDs for IOMMUFD vIOMMU instances Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 06/22] iommu/amd: Map vIOMMU VF and VF Control MMIO BARs Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 07/22] iommu/amd: Add support for AMD vIOMMU VF MMIO region Suravee Suthikulpanit
2026-07-07 14:33 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 08/22] iommu/amd: Introduce Reset vMMIO Command Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 09/22] iommu/amd: Introduce and map vIOMMU private IPA region Suravee Suthikulpanit
2026-07-07 14:07 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 10/22] iommu/amd: Pass iommu to device_flush_dte() Suravee Suthikulpanit
2026-07-07 14:18 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 11/22] iommu/amd: Export amd_iommu_alloc_dev_data() helper Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 12/22] iommu/amd: Pass iommu and devid to amd_iommu_make_clear_dte() Suravee Suthikulpanit
2026-07-07 14:20 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 13/22] iommu/amd: Assign IOMMU Private Address domain to IOMMU Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 14/22] iommu/amd: Add per-VM private IPA alloc/map helpers Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 15/22] iommu/amd: Add helper functions to manage DevID / DomID mapping tables Suravee Suthikulpanit
2026-06-29 15:35 ` [PATCH v3 16/22] iommu/amd: Introduce IOMMUFD vDevice support for AMD Suravee Suthikulpanit
2026-07-07 14:31 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 17/22] iommu/amd: Introduce helper function for updating domain ID mapping table Suravee Suthikulpanit
2026-07-07 14:32 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 18/22] iommu/amd: Introduce helper function for updating device " Suravee Suthikulpanit
2026-06-29 15:35 ` Suravee Suthikulpanit [this message]
2026-07-07 14:36 ` [PATCH v3 19/22] iommu/amd: Add per-segment translate device ID pool Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 20/22] iommu/amd: Reserve translate-device-id for PCI requestor aliases Suravee Suthikulpanit
2026-07-07 14:39 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 21/22] iommu/amd: Add translation DTE and VFctrl TransDevID helpers Suravee Suthikulpanit
2026-07-07 14:43 ` Jason Gunthorpe
2026-06-29 15:35 ` [PATCH v3 22/22] iommu/amd: Assign per-vIOMMU translate device ID Suravee Suthikulpanit
2026-07-07 14:45 ` [PATCH v3 00/22] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Jason Gunthorpe
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260629153535.15775-20-suravee.suthikulpanit@amd.com \
--to=suravee.suthikulpanit@amd.com \
--cc=chriscli@google.com \
--cc=dantuluris@google.com \
--cc=iommu@lists.linux.dev \
--cc=jay.chen@amd.com \
--cc=jgg@nvidia.com \
--cc=jon.grimm@amd.com \
--cc=joro@8bytes.org \
--cc=kevin.tian@intel.com \
--cc=kpsingh@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=nicolinc@nvidia.com \
--cc=sairaj.arunkodilkar@amd.com \
--cc=santosh.shukla@amd.com \
--cc=vasant.hegde@amd.com \
--cc=wnliu@google.com \
--cc=wvw@google.com \
--cc=yi.l.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox