Re: [PATCH v6 09/17] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports

["Bowman, Terry" <terry.bowman@amd.com>]

On 2/10/2025 2:16 PM, Gregory Price wrote:
> On Fri, Feb 07, 2025 at 06:29:33PM -0600, Terry Bowman wrote:
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index 4af39abbfab3..0adebf261fe7 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -652,7 +652,7 @@ void read_cdat_data(struct cxl_port *port)
>>  }
>>  EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL");
>>  
>> -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
>> +static void __cxl_handle_cor_ras(struct device *dev,
>>  				 void __iomem *ras_base)
>>  {
>>  	void __iomem *addr;
>> @@ -663,10 +663,8 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
>>  
>>  	addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
>>  	status = readl(addr);
>> -	if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) {
>> -		dev_err(cxl_dev, "%s():%d: CE Status is empty\n", __func__, __LINE__);
>> +	if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK))
>>  		return;
>> -	}
>>  	writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
>>  
>>  	if (is_cxl_memdev(cxl_dev))
>
> This seems like where you actually wanted this original change:

You're right. Somehow I moved a chunk into the wrong patch. I might need to respin this.

Terry
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index aa855c2068e0..a0c78655a8af 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -714,7 +714,7 @@ void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,
>  }
>  EXPORT_SYMBOL_NS_GPL(cxl_cper_trace_uncorr_port_prot_err, "CXL");
>  
> -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
> +static void __cxl_handle_cor_ras(struct device *dev,
>                                  void __iomem *ras_base)
>  {
>         void __iomem *addr;
> @@ -725,15 +725,19 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
>  
>         addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
>         status = readl(addr);
> -       if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> -               writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> -               trace_cxl_aer_correctable_error(cxlds->cxlmd, status);
> -       }
> +       if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK))
> +               return;
> +       writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> +
> +       if (is_cxl_memdev(dev))
> +               trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status);
> +       else if (is_cxl_port(dev))
> +               trace_cxl_port_aer_correctable_error(dev, status);
>  }