From: Gregory Price <gourry@gourry.net>
To: Terry Bowman <terry.bowman@amd.com>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, nifan.cxl@gmail.com,
dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, dan.j.williams@intel.com,
bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com,
oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com,
nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com,
lukas@wunner.de, ming.li@zohomail.com,
PradeepVineshReddy.Kodamati@amd.com
Subject: Re: [PATCH v6 06/17] PCI/AER: Add CXL PCIe Port uncorrectable error recovery in AER service driver
Date: Mon, 10 Feb 2025 13:43:58 -0500 [thread overview]
Message-ID: <Z6pI7oGXYyoecJzG@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <20250208002941.4135321-7-terry.bowman@amd.com>
On Fri, Feb 07, 2025 at 06:29:30PM -0600, Terry Bowman wrote:
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index a5c65f79db18..eda532f7440c 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -661,10 +661,16 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
>
> addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
> status = readl(addr);
> - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> - trace_cxl_aer_correctable_error(cxlds->cxlmd, status);
> + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) {
> + dev_err(cxl_dev, "%s():%d: CE Status is empty\n", __func__, __LINE__);
> + return;
> }
> + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> +
> + if (is_cxl_memdev(cxl_dev))
> + trace_cxl_aer_correctable_error(to_cxl_memdev(cxl_dev), status);
> + else if (is_cxl_port(cxl_dev))
> + trace_cxl_port_aer_correctable_error(cxl_dev, pcie_dev, status);
^^^^^^^^
Parameter isn't added until patch 14 - causes a build error.
~Gregory
next prev parent reply other threads:[~2025-02-10 18:44 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-08 0:29 [PATCH v6 00/17] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-02-08 0:29 ` [PATCH v6 01/17] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver' Terry Bowman
2025-02-08 0:29 ` [PATCH v6 02/17] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe Port support Terry Bowman
2025-02-08 0:29 ` [PATCH v6 03/17] CXL/PCI: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port() Terry Bowman
2025-02-08 0:29 ` [PATCH v6 04/17] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2025-02-08 0:29 ` [PATCH v6 05/17] PCI/AER: Add CXL PCIe Port correctable error support in AER service driver Terry Bowman
2025-02-08 0:29 ` [PATCH v6 06/17] PCI/AER: Add CXL PCIe Port uncorrectable error recovery " Terry Bowman
2025-02-10 18:43 ` Gregory Price [this message]
2025-02-10 20:13 ` Gregory Price
2025-02-08 0:29 ` [PATCH v6 07/17] cxl/pci: Map CXL PCIe Root Port and Downstream Switch Port RAS registers Terry Bowman
2025-02-08 0:29 ` [PATCH v6 08/17] cxl/pci: Map CXL PCIe Upstream " Terry Bowman
2025-02-08 0:29 ` [PATCH v6 09/17] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Terry Bowman
2025-02-10 20:16 ` Gregory Price
2025-02-10 20:36 ` Bowman, Terry
2025-02-08 0:29 ` [PATCH v6 10/17] cxl/pci: Add log message for unmapped registers in existing RAS handlers Terry Bowman
2025-02-08 0:29 ` [PATCH v6 11/17] cxl/pci: Change find_cxl_port() to non-static Terry Bowman
2025-02-08 0:29 ` [PATCH v6 12/17] cxl/pci: Add error handler for CXL PCIe Port RAS errors Terry Bowman
2025-02-08 0:29 ` [PATCH v6 13/17] cxl/pci: Add trace logging " Terry Bowman
2025-02-08 0:29 ` [PATCH v6 14/17] cxl/pci: Update CXL Port RAS logging to also display PCIe SBDF Terry Bowman
2025-02-08 0:29 ` [PATCH v6 15/17] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Terry Bowman
2025-02-08 0:29 ` [PATCH v6 16/17] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports Terry Bowman
2025-02-08 0:29 ` [PATCH v6 17/17] cxl/pci: Handle CXL Endpoint and RCH protocol errors separately from PCIe errors Terry Bowman
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