[PATCH 0/3] TLB flush fixes

[PATCH 0/3] TLB flush fixes

[Rik van Riel]

Some TLB flush fixes extracted from, or encountered while developing
the Intel RAR functionality.

1) Fix a potential overflow in user_pcid_flush_mask.
   I do not think anybody is hitting this in practice,
   but they could if they wanted to.

2) Change the early boot initialized value of invlpgb_count_max
   to 1, to avoid an infinite loop when...

3) Having cpa_flush() call flush_kernel_range(), which results
   in the INVPLGB code being called very early at boot time.

[PATCH 1/3] x86/mm: Fix potential overflow in user_pcid_flush_mask

[Rik van Riel]

From: Rik van Riel <riel@meta.com>

Currently no system with AMD INVLPGB support requires the page table
isolation mitigation. However, people could still enable PTI manually,
or a vulnerability could be found in the future that makes PTI useful
on certain AMD CPUs.

Additionally, there are systems that support Intel RAR TLB invalidation,
where PTI is a useful mitigation.

The combination of PTI and broadcast TLB flush has a problem:
- invalidate_user_asid() sets a bit corresponding to the process PCID in user_pcid_flush_mask
- SWITCH_TO_USER_CR3 tests and clears a bit corresponding to the process PCID in user_pcid_flush_mask

Enlarge user_pcid_flush_mask to fit the PCID numbers that can be present when
using broadcast TLB flushing. This takes up 256 or 512 bytes per CPU, depending
on whether or not page table isolation is built into the kernel.

Signed-off-by: Rik van Riel <riel@surriel.com>
Fixes: c3ed3f5b2550 x86/mm: userspace & pageout flushing using Intel RAR
Cc: stable@kernel.org
---
 arch/x86/include/asm/tlbflush.h | 42 ++++++++++++++++++++++++++-------
 arch/x86/kernel/asm-offsets.c   |  2 ++
 arch/x86/mm/tlb.c               | 28 +++-------------------
 3 files changed, 39 insertions(+), 33 deletions(-)

diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index e9b81876ebe4..cc9935bbbd45 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -23,6 +23,31 @@ void __flush_tlb_all(void);
 #define TLB_FLUSH_ALL	-1UL
 #define TLB_GENERATION_INVALID	0
 
+/*
+ * When enabled, MITIGATION_PAGE_TABLE_ISOLATION consumes a single bit for
+ * user/kernel switches
+ */
+#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
+# define PTI_CONSUMED_PCID_BITS	1
+#else
+# define PTI_CONSUMED_PCID_BITS	0
+#endif
+
+#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
+
+/*
+ * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
+ * for them being zero-based.  Another -1 is because PCID 0 is reserved for
+ * use by non-PCID-aware users.
+ */
+#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
+
+#ifdef CONFIG_BROADCAST_TLB_FLUSH
+# define CR3_AVAIL_PCID_LONGS ((1 << CR3_AVAIL_PCID_BITS) / BITS_PER_LONG)
+#else
+# define CR3_AVAIL_PCID_LONGS 1
+#endif
+
 void cr4_update_irqsoff(unsigned long set, unsigned long clear);
 unsigned long cr4_read_shadow(void);
 
@@ -115,14 +140,6 @@ struct tlb_state {
 	 */
 	u8 lam;
 #endif
-
-	/*
-	 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
-	 * the corresponding user PCID needs a flush next time we
-	 * switch to it; see SWITCH_TO_USER_CR3.
-	 */
-	unsigned short user_pcid_flush_mask;
-
 	/*
 	 * Access to this CR4 shadow and to H/W CR4 is protected by
 	 * disabling interrupts when modifying either one.
@@ -149,6 +166,15 @@ struct tlb_state {
 	 * context 0.
 	 */
 	struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
+
+#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
+	/*
+	 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
+	 * the corresponding user PCID needs a flush next time we
+	 * switch to it; see SWITCH_TO_USER_CR3.
+	 */
+	unsigned long user_pcid_flush_mask[CR3_AVAIL_PCID_LONGS];
+#endif
 };
 DECLARE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate);
 
diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c
index 6259b474073b..8c41a2e5a53e 100644
--- a/arch/x86/kernel/asm-offsets.c
+++ b/arch/x86/kernel/asm-offsets.c
@@ -103,8 +103,10 @@ static void __used common(void)
 	BLANK();
 	DEFINE(PTREGS_SIZE, sizeof(struct pt_regs));
 
+#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
 	/* TLB state for the entry code */
 	OFFSET(TLB_STATE_user_pcid_flush_mask, tlb_state, user_pcid_flush_mask);
+#endif
 
 	/* Layout info for cpu_entry_area */
 	OFFSET(CPU_ENTRY_AREA_entry_stack, cpu_entry_area, entry_stack_page);
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 39f80111e6f1..f5761e8be77f 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -90,25 +90,6 @@
  *
  */
 
-/*
- * When enabled, MITIGATION_PAGE_TABLE_ISOLATION consumes a single bit for
- * user/kernel switches
- */
-#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
-# define PTI_CONSUMED_PCID_BITS	1
-#else
-# define PTI_CONSUMED_PCID_BITS	0
-#endif
-
-#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
-
-/*
- * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
- * for them being zero-based.  Another -1 is because PCID 0 is reserved for
- * use by non-PCID-aware users.
- */
-#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
-
 /*
  * Given @asid, compute kPCID
  */
@@ -543,10 +524,7 @@ static void broadcast_tlb_flush(struct flush_tlb_info *info)
  */
 static inline void invalidate_user_asid(u16 asid)
 {
-	/* There is no user ASID if address space separation is off */
-	if (!IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION))
-		return;
-
+#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
 	/*
 	 * We only have a single ASID if PCID is off and the CR3
 	 * write will have flushed it.
@@ -557,8 +535,8 @@ static inline void invalidate_user_asid(u16 asid)
 	if (!static_cpu_has(X86_FEATURE_PTI))
 		return;
 
-	__set_bit(kern_pcid(asid),
-		  (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
+	__set_bit(kern_pcid(asid), this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask[0]));
+#endif
 }
 
 static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, unsigned long lam,
-- 
2.49.0

[PATCH 2/3] x86/mm: Fix early boot use of INVPLGB

[Rik van Riel]

Use of the INVLPGB instruction is done based off the X86_FEATURE_INVLPGB
CPU feature, which is provided directly by the hardware.

If invlpgb_kernel_range_flush is called before the kernel has read
the value of invlpgb_count_max from the hardware, the normally
bounded loop can become an infinite loop if invlpgb_count_max is
initialized to zero.

Fix that issue by initializing invlpgb_count_max to 1.

This way INVPLGB at early boot time will be a little bit slower
than normal (with initialized invplgb_count_max), and not an
instant hang at bootup time.

Signed-off-by: Rik van Riel <riel@surriel.com>
Fixes: b7aa05cbdc52 ("x86/mm: Add INVLPGB support code")
Cc: stable@kernel.org
---
 arch/x86/kernel/cpu/amd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 93da466dfe2c..b2ad8d13211a 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -31,7 +31,7 @@
 
 #include "cpu.h"
 
-u16 invlpgb_count_max __ro_after_init;
+u16 invlpgb_count_max __ro_after_init = 1;
 
 static inline int rdmsrq_amd_safe(unsigned msr, u64 *p)
 {
-- 
2.49.0

[PATCH 3/3] x86/mm: Change cpa_flush() to call flush_kernel_range() directly

[Rik van Riel]

From: Yu-cheng Yu <yu-cheng.yu@intel.com>

The function cpa_flush() calls __flush_tlb_one_kernel() and
flush_tlb_all().

Replacing that with a call to flush_tlb_kernel_range() allows
cpa_flush() to make use of INVLPGB or RAR without any additional
changes.

Initialize invlpgb_count_max to 1, since flush_tlb_kernel_range()
can now be called before invlpgb_count_max has been initialized
to the value read from CPUID.

[riel: remove now unused __cpa_flush_tlb]

Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rik van Riel <riel@surriel.com>
---
 arch/x86/mm/pat/set_memory.c | 20 +++++++-------------
 1 file changed, 7 insertions(+), 13 deletions(-)

diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index 30ab4aced761..2454f5249329 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -399,15 +399,6 @@ static void cpa_flush_all(unsigned long cache)
 	on_each_cpu(__cpa_flush_all, (void *) cache, 1);
 }
 
-static void __cpa_flush_tlb(void *data)
-{
-	struct cpa_data *cpa = data;
-	unsigned int i;
-
-	for (i = 0; i < cpa->numpages; i++)
-		flush_tlb_one_kernel(fix_addr(__cpa_addr(cpa, i)));
-}
-
 static int collapse_large_pages(unsigned long addr, struct list_head *pgtables);
 
 static void cpa_collapse_large_pages(struct cpa_data *cpa)
@@ -444,6 +435,7 @@ static void cpa_collapse_large_pages(struct cpa_data *cpa)
 
 static void cpa_flush(struct cpa_data *cpa, int cache)
 {
+	unsigned long start, end;
 	unsigned int i;
 
 	BUG_ON(irqs_disabled() && !early_boot_irqs_disabled);
@@ -453,10 +445,12 @@ static void cpa_flush(struct cpa_data *cpa, int cache)
 		goto collapse_large_pages;
 	}
 
-	if (cpa->force_flush_all || cpa->numpages > tlb_single_page_flush_ceiling)
-		flush_tlb_all();
-	else
-		on_each_cpu(__cpa_flush_tlb, cpa, 1);
+	start = fix_addr(__cpa_addr(cpa, 0));
+	end = fix_addr(__cpa_addr(cpa, cpa->numpages));
+	if (cpa->force_flush_all)
+		end = TLB_FLUSH_ALL;
+
+	flush_tlb_kernel_range(start, end);
 
 	if (!cache)
 		goto collapse_large_pages;
-- 
2.49.0

Re: [PATCH 1/3] x86/mm: Fix potential overflow in user_pcid_flush_mask

[Dave Hansen]

On 6/2/25 06:30, Rik van Riel wrote:
> Currently no system with AMD INVLPGB support requires the page table
> isolation mitigation. However, people could still enable PTI manually,
> or a vulnerability could be found in the future that makes PTI useful
> on certain AMD CPUs.
> 
> Additionally, there are systems that support Intel RAR TLB invalidation,
> where PTI is a useful mitigation.

Let's just leave this mention of RAR out for now.

> The combination of PTI and broadcast TLB flush has a problem:
> - invalidate_user_asid() sets a bit corresponding to the process PCID in user_pcid_flush_mask
> - SWITCH_TO_USER_CR3 tests and clears a bit corresponding to the process PCID in user_pcid_flush_mask

The other bit of background here is that there are currently only 6
PCIDs that might need to be flushed in this way (TLB_NR_DYN_ASIDS).
There are obviously more than 6 bits in an unsigned long, so this is all
fine.

But the INVLPGB support vastly expanded the number of ASIDs that might
be used.

> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
> index e9b81876ebe4..cc9935bbbd45 100644
> --- a/arch/x86/include/asm/tlbflush.h
> +++ b/arch/x86/include/asm/tlbflush.h
> @@ -23,6 +23,31 @@ void __flush_tlb_all(void);
>  #define TLB_FLUSH_ALL	-1UL
>  #define TLB_GENERATION_INVALID	0
>  
> +/*
> + * When enabled, MITIGATION_PAGE_TABLE_ISOLATION consumes a single bit for
> + * user/kernel switches
> + */
> +#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
> +# define PTI_CONSUMED_PCID_BITS	1
> +#else
> +# define PTI_CONSUMED_PCID_BITS	0
> +#endif
> +
> +#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
> +
> +/*
> + * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
> + * for them being zero-based.  Another -1 is because PCID 0 is reserved for
> + * use by non-PCID-aware users.
> + */
> +#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
> +
> +#ifdef CONFIG_BROADCAST_TLB_FLUSH
> +# define CR3_AVAIL_PCID_LONGS ((1 << CR3_AVAIL_PCID_BITS) / BITS_PER_LONG)
> +#else
> +# define CR3_AVAIL_PCID_LONGS 1
> +#endif

I wonder if we can make this easier to understand. Is there something
preventing us from using good old DECLARE_BITMAP()?

	DECLARE_BITMAP(user_pcid_flush_mask, MAX_KERN_ASID);

#ifdef CONFIG_BROADCAST_TLB_FLUSH
# define MAX_KERN_PCID (1 << CR3_AVAIL_PCID_BITS - 1)
#else
  /* PCID 0 is reserved. Dynamic asids 0->5 map to PCIDs 1->6 */
# define MAX_KERN_PCID (TLB_NR_DYN_ASIDS + 1)
#endif

The TLB_NR_DYN_ASIDS portion of this could even be a preparatory patch
before the CONFIG_BROADCAST_TLB_FLUSH gets added. That might also make
the whole thing more clear.

>  void cr4_update_irqsoff(unsigned long set, unsigned long clear);
>  unsigned long cr4_read_shadow(void);
>  
> @@ -115,14 +140,6 @@ struct tlb_state {
>  	 */
>  	u8 lam;
>  #endif
> -
> -	/*
> -	 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
> -	 * the corresponding user PCID needs a flush next time we
> -	 * switch to it; see SWITCH_TO_USER_CR3.
> -	 */
> -	unsigned short user_pcid_flush_mask;
> -
>  	/*
>  	 * Access to this CR4 shadow and to H/W CR4 is protected by
>  	 * disabling interrupts when modifying either one.
> @@ -149,6 +166,15 @@ struct tlb_state {
>  	 * context 0.
>  	 */
>  	struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
> +
> +#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
> +	/*
> +	 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
> +	 * the corresponding user PCID needs a flush next time we
> +	 * switch to it; see SWITCH_TO_USER_CR3.
> +	 */
> +	unsigned long user_pcid_flush_mask[CR3_AVAIL_PCID_LONGS];
> +#endif
>  };
>  DECLARE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate);

This adds an #ifdef. I guess it makes sense to do it for the now larger
user_pcid_flush_mask[] while it didn't for a single long. But that's
another logically separate bit that adds complexity to reading this
whole mess.

Honestly, I'd just leave this out for the bug fix. If someone really
cares, we can come back and fix it up in mainline.

> diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c
> index 6259b474073b..8c41a2e5a53e 100644
> --- a/arch/x86/kernel/asm-offsets.c
> +++ b/arch/x86/kernel/asm-offsets.c
> @@ -103,8 +103,10 @@ static void __used common(void)
>  	BLANK();
>  	DEFINE(PTREGS_SIZE, sizeof(struct pt_regs));
>  
> +#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
>  	/* TLB state for the entry code */
>  	OFFSET(TLB_STATE_user_pcid_flush_mask, tlb_state, user_pcid_flush_mask);
> +#endif

Because it necessitates this hunk too...

>  	/* Layout info for cpu_entry_area */
>  	OFFSET(CPU_ENTRY_AREA_entry_stack, cpu_entry_area, entry_stack_page);
> diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
> index 39f80111e6f1..f5761e8be77f 100644
> --- a/arch/x86/mm/tlb.c
> +++ b/arch/x86/mm/tlb.c
> @@ -90,25 +90,6 @@
>   *
>   */
>  
> -/*
> - * When enabled, MITIGATION_PAGE_TABLE_ISOLATION consumes a single bit for
> - * user/kernel switches
> - */
> -#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
> -# define PTI_CONSUMED_PCID_BITS	1
> -#else
> -# define PTI_CONSUMED_PCID_BITS	0
> -#endif
> -
> -#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
> -
> -/*
> - * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
> - * for them being zero-based.  Another -1 is because PCID 0 is reserved for
> - * use by non-PCID-aware users.
> - */
> -#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
> -
>  /*
>   * Given @asid, compute kPCID
>   */
> @@ -543,10 +524,7 @@ static void broadcast_tlb_flush(struct flush_tlb_info *info)
>   */
>  static inline void invalidate_user_asid(u16 asid)
>  {
> -	/* There is no user ASID if address space separation is off */
> -	if (!IS_ENABLED(CONFIG_MITIGATION_PAGE_TABLE_ISOLATION))
> -		return;
> -
> +#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
>  	/*
>  	 * We only have a single ASID if PCID is off and the CR3
>  	 * write will have flushed it.
> @@ -557,8 +535,8 @@ static inline void invalidate_user_asid(u16 asid)
>  	if (!static_cpu_has(X86_FEATURE_PTI))
>  		return;
>  
> -	__set_bit(kern_pcid(asid),
> -		  (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
> +	__set_bit(kern_pcid(asid), this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask[0]));
> +#endif
>  }
... and this one.

Re: [PATCH 2/3] x86/mm: Fix early boot use of INVPLGB

[Dave Hansen]

On 6/2/25 06:30, Rik van Riel wrote:
> Use of the INVLPGB instruction is done based off the X86_FEATURE_INVLPGB
> CPU feature, which is provided directly by the hardware.
> 
> If invlpgb_kernel_range_flush is called before the kernel has read
> the value of invlpgb_count_max from the hardware, the normally
> bounded loop can become an infinite loop if invlpgb_count_max is
> initialized to zero.
> 
> Fix that issue by initializing invlpgb_count_max to 1.
> 
> This way INVPLGB at early boot time will be a little bit slower
> than normal (with initialized invplgb_count_max), and not an
> instant hang at bootup time.

The INVLPGB instruction has limits on how many invalidations it can
perform at once. That limit is enumerated in CPUID, read by the kernel,
and stored in 'invlpgb_count_max'. Ranged invalidation (like
invlpgb_kernel_range_flush()) break up their invalidations so that they
do not exceed the limit.

However, early boot code currently attempts to do ranged invalidations
before populating 'invlpgb_count_max'. There's a for() loop which is
basically:

	for (...; addr < end; addr += invlpgb_count_max*PAGE_SIZE)

It doesn't make much progress when invlpgb_count_max==0.

... then the rest

---

BTW, how was this code even _working_ without this patch? Are the early
boot ranged invalidations infrequent or something?

Acked-by: Dave Hansen <dave.hansen@linux.intel.com>

Re: [PATCH 3/3] x86/mm: Change cpa_flush() to call flush_kernel_range() directly

[Dave Hansen]

On 6/2/25 06:30, Rik van Riel wrote:
> From: Yu-cheng Yu <yu-cheng.yu@intel.com>
> 
> The function cpa_flush() calls __flush_tlb_one_kernel() and
> flush_tlb_all().
> 
> Replacing that with a call to flush_tlb_kernel_range() allows
> cpa_flush() to make use of INVLPGB or RAR without any additional
> changes.
> 
> Initialize invlpgb_count_max to 1, since flush_tlb_kernel_range()
> can now be called before invlpgb_count_max has been initialized
> to the value read from CPUID.

Looks good, thanks for picking this out of the RAR series:

Acked-by: Dave Hansen <dave.hansen@linux.intel.com>

Re: [PATCH 1/3] x86/mm: Fix potential overflow in user_pcid_flush_mask

[Rik van Riel]

On Mon, 2025-06-02 at 09:55 -0700, Dave Hansen wrote:
> On 6/2/25 06:30, Rik van Riel wrote:
> > 
> > @@ -149,6 +166,15 @@ struct tlb_state {
> >  	 * context 0.
> >  	 */
> >  	struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
> > +
> > +#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
> > +	/*
> > +	 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
> > +	 * the corresponding user PCID needs a flush next time we
> > +	 * switch to it; see SWITCH_TO_USER_CR3.
> > +	 */
> > +	unsigned long user_pcid_flush_mask[CR3_AVAIL_PCID_LONGS];
> > +#endif
> >  };
> >  DECLARE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate);
> 
> This adds an #ifdef. I guess it makes sense to do it for the now
> larger
> user_pcid_flush_mask[] while it didn't for a single long. But that's
> another logically separate bit that adds complexity to reading this
> whole mess.
> 
> Honestly, I'd just leave this out for the bug fix. If someone really
> cares, we can come back and fix it up in mainline.

I added the #ifdef at Ingo's request.

I am happy to do the code in any way you two can
agree on, but we should probably avoid the back
and forth over many versions thing :)

> 
> > diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-
> > offsets.c
> > index 6259b474073b..8c41a2e5a53e 100644
> > --- a/arch/x86/kernel/asm-offsets.c
> > +++ b/arch/x86/kernel/asm-offsets.c
> > @@ -103,8 +103,10 @@ static void __used common(void)
> >  	BLANK();
> >  	DEFINE(PTREGS_SIZE, sizeof(struct pt_regs));
> >  
> > +#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
> >  	/* TLB state for the entry code */
> >  	OFFSET(TLB_STATE_user_pcid_flush_mask, tlb_state,
> > user_pcid_flush_mask);
> > +#endif
> 
> Because it necessitates this hunk too...

I agree this isn't the prettiest, but then again
asm-offsets.c isn't code people will be reading
a lot?


-- 
All Rights Reversed.

Re: [PATCH 1/3] x86/mm: Fix potential overflow in user_pcid_flush_mask

[Dave Hansen]

On 6/3/25 14:20, Rik van Riel wrote:
>> Honestly, I'd just leave this out for the bug fix. If someone really
>> cares, we can come back and fix it up in mainline.
> I added the #ifdef at Ingo's request.
> 
> I am happy to do the code in any way you two can
> agree on, but we should probably avoid the back
> and forth over many versions thing 🙂

Ingo, I don't think the #ifdef is worth it, especially for what needs to
go to stable@. The PTI config option is enabled quite widely, so it's
not doing much practically. If you feel strongly that it's required for
this series, then it needs to be broken out as a prerequisite and not
intermingled with the actual bug fix.