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* [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events
@ 2025-05-16 13:43 tip-bot2 for Sandipan Das
  2025-05-16 14:18 ` Vince Weaver
  0 siblings, 1 reply; 4+ messages in thread
From: tip-bot2 for Sandipan Das @ 2025-05-16 13:43 UTC (permalink / raw)
  To: linux-tip-commits
  Cc: Sandipan Das, Ingo Molnar, Peter Zijlstra, linux-perf-users, x86,
	linux-kernel

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     ebe176981c14b5f6472718f9894db35816749120
Gitweb:        https://git.kernel.org/tip/ebe176981c14b5f6472718f9894db35816749120
Author:        Sandipan Das <sandipan.das@amd.com>
AuthorDate:    Wed, 07 May 2025 17:42:04 +05:30
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Fri, 16 May 2025 15:32:59 +02:00

perf/x86/amd/core: Fix Family 17h+ instruction cache events

PMCx080 and PMCx081 report incorrect IC accesses and misses respectively
for all Family 17h and later processors. PMCx060 unit mask 0x10 replaces
PMCx081 for counting IC misses but there is no suitable replacement for
counting IC accesses.

Fixes: 0e3b74e26280 ("perf/x86/amd: Update generic hardware cache events for Family 17h")
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-perf-users@vger.kernel.org
Link: https://lore.kernel.org/r/2f475a1ba4b240111e69644fc2d5bf93b2e39c99.1746618724.git.sandipan.das@amd.com
---
 arch/x86/events/amd/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 30d6ceb..52860b9 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -148,8 +148,8 @@ static __initconst const u64 amd_hw_cache_event_ids_f17h
 },
 [C(L1I)] = {
 	[C(OP_READ)] = {
-		[C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches  */
-		[C(RESULT_MISS)]   = 0x0081, /* Instruction cache misses   */
+		[C(RESULT_ACCESS)] = 0,
+		[C(RESULT_MISS)]   = 0x1060, /* L2$ access from IC Miss */
 	},
 	[C(OP_WRITE)] = {
 		[C(RESULT_ACCESS)] = -1,

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events
  2025-05-16 13:43 [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events tip-bot2 for Sandipan Das
@ 2025-05-16 14:18 ` Vince Weaver
  2025-05-17 13:02   ` Ingo Molnar
  0 siblings, 1 reply; 4+ messages in thread
From: Vince Weaver @ 2025-05-16 14:18 UTC (permalink / raw)
  To: linux-kernel
  Cc: linux-tip-commits, Sandipan Das, Ingo Molnar, Peter Zijlstra,
	linux-perf-users, x86

On Fri, 16 May 2025, tip-bot2 for Sandipan Das wrote:

> The following commit has been merged into the perf/urgent branch of tip:
> 

> perf/x86/amd/core: Fix Family 17h+ instruction cache events
> 
> PMCx080 and PMCx081 report incorrect IC accesses and misses respectively
> for all Family 17h and later processors. PMCx060 unit mask 0x10 replaces
> PMCx081 for counting IC misses but there is no suitable replacement for
> counting IC accesses.

can you link to the errata document that describes this problem as well as 
maybe give a rundown of how and why this breaks?

Vince Weaver
vincent.weaver@maine.edu

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events
  2025-05-16 14:18 ` Vince Weaver
@ 2025-05-17 13:02   ` Ingo Molnar
  2025-05-21  5:30     ` Sandipan Das
  0 siblings, 1 reply; 4+ messages in thread
From: Ingo Molnar @ 2025-05-17 13:02 UTC (permalink / raw)
  To: Vince Weaver
  Cc: linux-kernel, linux-tip-commits, Sandipan Das, Peter Zijlstra,
	linux-perf-users, x86


* Vince Weaver <vincent.weaver@maine.edu> wrote:

> On Fri, 16 May 2025, tip-bot2 for Sandipan Das wrote:
> 
> > The following commit has been merged into the perf/urgent branch of tip:
> > 
> 
> > perf/x86/amd/core: Fix Family 17h+ instruction cache events
> > 
> > PMCx080 and PMCx081 report incorrect IC accesses and misses respectively
> > for all Family 17h and later processors. PMCx060 unit mask 0x10 replaces
> > PMCx081 for counting IC misses but there is no suitable replacement for
> > counting IC accesses.
> 
> can you link to the errata document that describes this problem as well as 
> maybe give a rundown of how and why this breaks?

I've delayed this patch until these details are cleared up.

Thanks,

	Ingo

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events
  2025-05-17 13:02   ` Ingo Molnar
@ 2025-05-21  5:30     ` Sandipan Das
  0 siblings, 0 replies; 4+ messages in thread
From: Sandipan Das @ 2025-05-21  5:30 UTC (permalink / raw)
  To: Ingo Molnar, Vince Weaver
  Cc: linux-kernel, linux-tip-commits, Peter Zijlstra, linux-perf-users,
	x86

On 5/17/2025 6:32 PM, Ingo Molnar wrote:
> 
> * Vince Weaver <vincent.weaver@maine.edu> wrote:
> 
>> On Fri, 16 May 2025, tip-bot2 for Sandipan Das wrote:
>>
>>> The following commit has been merged into the perf/urgent branch of tip:
>>>
>>
>>> perf/x86/amd/core: Fix Family 17h+ instruction cache events
>>>
>>> PMCx080 and PMCx081 report incorrect IC accesses and misses respectively
>>> for all Family 17h and later processors. PMCx060 unit mask 0x10 replaces
>>> PMCx081 for counting IC misses but there is no suitable replacement for
>>> counting IC accesses.
>>
>> can you link to the errata document that describes this problem as well as 
>> maybe give a rundown of how and why this breaks?
> 
> I've delayed this patch until these details are cleared up.
> 

Both of these events were removed from the Processor Programming Reference
starting with Zen 2. Errata is missing for Zen 1 but it is known that these
events are broken. A quick test like the following will show that PMCx081
undercounts IC misses compared to PMCx060 with unit mask 0x10.

$ perf stat -e "{cpu/event=0x81/,cpu/event=0x60,umask=0x10/}" ./ic-miss

 Performance counter stats for './ic-miss':

             2,105      cpu/event=0x81/u
            30,826      cpu/event=0x60,umask=0x10/u

       1.650143599 seconds time elapsed

       1.646070000 seconds user
       0.000998000 seconds sys

If its acceptable, I can send out a v2 with the details above.

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2025-05-21  5:31 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2025-05-16 13:43 [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events tip-bot2 for Sandipan Das
2025-05-16 14:18 ` Vince Weaver
2025-05-17 13:02   ` Ingo Molnar
2025-05-21  5:30     ` Sandipan Das

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