RE: [PATCH v2 4/4] iommu/arm: Add BBM Level 2 smmu feature

[Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>]

> -----Original Message-----
> From: Jason Gunthorpe <jgg@ziepe.ca>
> Sent: Friday, February 28, 2025 7:32 PM
> To: Mikołaj Lenczewski <miko.lenczewski@arm.com>; Shameerali Kolothum
> Thodi <shameerali.kolothum.thodi@huawei.com>
> Cc: ryan.roberts@arm.com; suzuki.poulose@arm.com;
> yang@os.amperecomputing.com; catalin.marinas@arm.com;
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> Subject: Re: [PATCH v2 4/4] iommu/arm: Add BBM Level 2 smmu feature
> 
> On Fri, Feb 28, 2025 at 06:24:04PM +0000, Mikołaj Lenczewski wrote:
> > For supporting BBM Level 2 for userspace mappings, we want to ensure
> > that the smmu also supports its own version of BBM Level 2. Luckily, the
> > smmu spec (IHI 0070G 3.21.1.3) is stricter than the aarch64 spec (DDI
> > 0487K.a D8.16.2), so already guarantees that no aborts are raised when
> > BBM level 2 is claimed.
> >
> > Add the feature and testing for it under arm_smmu_sva_supported().
> >
> > Signed-off-by: Mikołaj Lenczewski <miko.lenczewski@arm.com>
> > ---
> >  arch/arm64/kernel/cpufeature.c                  | 7 +++----
> >  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 3 +++
> >  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c     | 3 +++
> >  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h     | 4 ++++
> >  4 files changed, 13 insertions(+), 4 deletions(-)
> 
> This patch looks good, for what it does. However for bisection safety
> it should be earlier, before the patches that change the page table
> algorithms to be unsafe for the SMMU.
> 
> However, I've heard people talking about shipping chips that have CPUs
> with BBML2 but SMMUs without.
> 
> On such a system it seems like your series would break previously
> working SVA support because this patch will end up disabling it?
> 
> Though I see your MIDR_REV list is limited, so perhaps that worry
> doesn't effect any real chips made with those families? I am trying to
> check some NVIDIA products against this list..

We do have implementations that support CPUs with BBLM2 with TLB
conflict aborts and SMMUv3 with BBML2.  So don't think those platforms
be affected by this.  Will check with our hardware folks if there is
anything that will be affected by this.

Also we  have plans to try to use SMMUv3 BBML2 during VM live migration
to split block pages to 4K. I guess, in that case we can enable SMMU BBML2
independent of CPU side. 

Thanks,
Shameer