* [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
@ 2024-08-01 10:57 Amandeep Singh
0 siblings, 0 replies; 7+ messages in thread
From: Amandeep Singh @ 2024-08-01 10:57 UTC (permalink / raw)
To: andersson, mturquette, sboyd, linux-arm-msm, linux-clk,
linux-kernel
Cc: quic_devipriy
From: devi priya <quic_devipriy@quicinc.com>
Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
---
drivers/clk/qcom/gcc-ipq9574.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 80fc94d705a0..645109f75b46 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -68,7 +68,7 @@ static const struct clk_parent_data gcc_sleep_clk_data[] = {
static struct clk_alpha_pll gpll0_main = {
.offset = 0x20000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(0),
@@ -96,7 +96,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x20000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll0",
@@ -110,7 +110,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
static struct clk_alpha_pll gpll4_main = {
.offset = 0x22000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(2),
@@ -125,7 +125,7 @@ static struct clk_alpha_pll gpll4_main = {
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x22000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll4",
@@ -139,7 +139,7 @@ static struct clk_alpha_pll_postdiv gpll4 = {
static struct clk_alpha_pll gpll2_main = {
.offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(1),
@@ -154,7 +154,7 @@ static struct clk_alpha_pll gpll2_main = {
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll2",
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
@ 2024-08-01 11:00 Amandeep Singh
2024-08-03 1:05 ` Stephen Boyd
0 siblings, 1 reply; 7+ messages in thread
From: Amandeep Singh @ 2024-08-01 11:00 UTC (permalink / raw)
To: andersson, mturquette, sboyd, linux-arm-msm, linux-clk,
linux-kernel
Cc: quic_devipriy
From: devi priya <quic_devipriy@quicinc.com>
Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
---
drivers/clk/qcom/gcc-ipq9574.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 80fc94d705a0..645109f75b46 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -68,7 +68,7 @@ static const struct clk_parent_data gcc_sleep_clk_data[] = {
static struct clk_alpha_pll gpll0_main = {
.offset = 0x20000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(0),
@@ -96,7 +96,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x20000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll0",
@@ -110,7 +110,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
static struct clk_alpha_pll gpll4_main = {
.offset = 0x22000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(2),
@@ -125,7 +125,7 @@ static struct clk_alpha_pll gpll4_main = {
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x22000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll4",
@@ -139,7 +139,7 @@ static struct clk_alpha_pll_postdiv gpll4 = {
static struct clk_alpha_pll gpll2_main = {
.offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(1),
@@ -154,7 +154,7 @@ static struct clk_alpha_pll gpll2_main = {
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll2",
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
2024-08-01 11:00 [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs Amandeep Singh
@ 2024-08-03 1:05 ` Stephen Boyd
2024-08-05 9:11 ` Amandeep Singh
0 siblings, 1 reply; 7+ messages in thread
From: Stephen Boyd @ 2024-08-03 1:05 UTC (permalink / raw)
To: Amandeep Singh, andersson, linux-arm-msm, linux-clk, linux-kernel,
mturquette
Cc: quic_devipriy
Quoting Amandeep Singh (2024-08-01 04:00:40)
> From: devi priya <quic_devipriy@quicinc.com>
>
> Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
Is this fixing a problem? I can't figure out how urgent this patch is
from the one sentence commit text.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
2024-08-03 1:05 ` Stephen Boyd
@ 2024-08-05 9:11 ` Amandeep Singh
2024-08-05 17:58 ` Stephen Boyd
0 siblings, 1 reply; 7+ messages in thread
From: Amandeep Singh @ 2024-08-05 9:11 UTC (permalink / raw)
To: Stephen Boyd, andersson, linux-arm-msm, linux-clk, linux-kernel,
mturquette
Cc: quic_devipriy
On 8/3/2024 6:35 AM, Stephen Boyd wrote:
> Quoting Amandeep Singh (2024-08-01 04:00:40)
>> From: devi priya <quic_devipriy@quicinc.com>
>>
>> Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
>
> Is this fixing a problem? I can't figure out how urgent this patch is
> from the one sentence commit text.
The incorrect clock frequency leads to an incorrect MDIO clock. This,
in turn, affects the MDIO hardware configurations as the divider is
calculated from the MDIO clock frequency. If the clock frequency is
not as expected, the MDIO register fails due to the generation of an
incorrect MDIO frequency.
This issue is critical as it results in incorrect MDIO configurations
and ultimately leads to the MDIO function not working. This results in
a complete feature failure affecting all Ethernet PHYs. Specifically,
Ethernet will not work on IPQ9574 due to this issue.
Currently, the clock frequency is set to CLK_ALPHA_PLL_TYPE_DEFAULT.
However, this setting does not yield the expected clock frequency. To
rectify this, we need to change this to CLK_ALPHA_PLL_TYPE_DEFAULT_EVO.
This modification ensures that the clock frequency aligns with our
expectations, thereby resolving the MDIO register failure and ensuring
the proper functioning of the Ethernet on IPQ9574.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
2024-08-05 9:11 ` Amandeep Singh
@ 2024-08-05 17:58 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2024-08-05 17:58 UTC (permalink / raw)
To: Amandeep Singh, andersson, linux-arm-msm, linux-clk, linux-kernel,
mturquette
Cc: quic_devipriy
Quoting Amandeep Singh (2024-08-05 02:11:16)
> On 8/3/2024 6:35 AM, Stephen Boyd wrote:
> > Quoting Amandeep Singh (2024-08-01 04:00:40)
> >> From: devi priya <quic_devipriy@quicinc.com>
> >>
> >> Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
> >
> > Is this fixing a problem? I can't figure out how urgent this patch is
> > from the one sentence commit text.
>
> The incorrect clock frequency leads to an incorrect MDIO clock. This,
> in turn, affects the MDIO hardware configurations as the divider is
> calculated from the MDIO clock frequency. If the clock frequency is
> not as expected, the MDIO register fails due to the generation of an
> incorrect MDIO frequency.
>
> This issue is critical as it results in incorrect MDIO configurations
> and ultimately leads to the MDIO function not working. This results in
> a complete feature failure affecting all Ethernet PHYs. Specifically,
> Ethernet will not work on IPQ9574 due to this issue.
>
> Currently, the clock frequency is set to CLK_ALPHA_PLL_TYPE_DEFAULT.
> However, this setting does not yield the expected clock frequency. To
> rectify this, we need to change this to CLK_ALPHA_PLL_TYPE_DEFAULT_EVO.
>
> This modification ensures that the clock frequency aligns with our
> expectations, thereby resolving the MDIO register failure and ensuring
> the proper functioning of the Ethernet on IPQ9574.
Wow! Please include these details in the commit text.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
@ 2024-08-06 6:11 Amandeep Singh
2024-08-15 20:40 ` Bjorn Andersson
0 siblings, 1 reply; 7+ messages in thread
From: Amandeep Singh @ 2024-08-06 6:11 UTC (permalink / raw)
To: andersson, mturquette, sboyd, linux-arm-msm, linux-clk,
linux-kernel
Cc: quic_devipriy
From: devi priya <quic_devipriy@quicinc.com>
Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
The incorrect clock frequency leads to an incorrect MDIO clock. This,
in turn, affects the MDIO hardware configurations as the divider is
calculated from the MDIO clock frequency. If the clock frequency is
not as expected, the MDIO register fails due to the generation of an
incorrect MDIO frequency.
This issue is critical as it results in incorrect MDIO configurations
and ultimately leads to the MDIO function not working. This results in
a complete feature failure affecting all Ethernet PHYs. Specifically,
Ethernet will not work on IPQ9574 due to this issue.
Currently, the clock frequency is set to CLK_ALPHA_PLL_TYPE_DEFAULT.
However, this setting does not yield the expected clock frequency.
To rectify this, we need to change this to CLK_ALPHA_PLL_TYPE_DEFAULT_EVO.
This modification ensures that the clock frequency aligns with our
expectations, thereby resolving the MDIO register failure and ensuring
the proper functioning of the Ethernet on IPQ9574.
Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
---
drivers/clk/qcom/gcc-ipq9574.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 80fc94d705a0..645109f75b46 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -68,7 +68,7 @@ static const struct clk_parent_data gcc_sleep_clk_data[] = {
static struct clk_alpha_pll gpll0_main = {
.offset = 0x20000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(0),
@@ -96,7 +96,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x20000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll0",
@@ -110,7 +110,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
static struct clk_alpha_pll gpll4_main = {
.offset = 0x22000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(2),
@@ -125,7 +125,7 @@ static struct clk_alpha_pll gpll4_main = {
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x22000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll4",
@@ -139,7 +139,7 @@ static struct clk_alpha_pll_postdiv gpll4 = {
static struct clk_alpha_pll gpll2_main = {
.offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(1),
@@ -154,7 +154,7 @@ static struct clk_alpha_pll gpll2_main = {
static struct clk_alpha_pll_postdiv gpll2 = {
.offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpll2",
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
2024-08-06 6:11 Amandeep Singh
@ 2024-08-15 20:40 ` Bjorn Andersson
0 siblings, 0 replies; 7+ messages in thread
From: Bjorn Andersson @ 2024-08-15 20:40 UTC (permalink / raw)
To: mturquette, sboyd, linux-arm-msm, linux-clk, linux-kernel,
Amandeep Singh
Cc: quic_devipriy
On Tue, 06 Aug 2024 11:41:05 +0530, Amandeep Singh wrote:
> Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
>
> The incorrect clock frequency leads to an incorrect MDIO clock. This,
> in turn, affects the MDIO hardware configurations as the divider is
> calculated from the MDIO clock frequency. If the clock frequency is
> not as expected, the MDIO register fails due to the generation of an
> incorrect MDIO frequency.
>
> [...]
Applied, thanks!
[1/1] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs
commit: 6357efe3abead68048729adf11a9363881657939
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-08-15 20:41 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-08-01 11:00 [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs Amandeep Singh
2024-08-03 1:05 ` Stephen Boyd
2024-08-05 9:11 ` Amandeep Singh
2024-08-05 17:58 ` Stephen Boyd
-- strict thread matches above, loose matches on Subject: below --
2024-08-06 6:11 Amandeep Singh
2024-08-15 20:40 ` Bjorn Andersson
2024-08-01 10:57 Amandeep Singh
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox