[PATCH] can: m_can: Implement workaround for errata i2278 and i2279

[PATCH] can: m_can: Implement workaround for errata i2278 and i2279

[Anurag Dutta]

Message transmit order is not guaranteed when dedicated TX buffers
configured with the same Message ID are submitted simultaneously via
TXBAR write. This is described in J7 errata i2278 and i2279.

As a workaround, introduce m_can_tx_peripheral_submit() to submit
buffers one at a time using ffs() to find the next pending buffer.
The TX complete interrupt(IR_TC) triggers submission of the next
buffer, ensuring strict FIFO ordering.

Link: https://www.ti.com/lit/pdf/sprz530
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
---

 drivers/net/can/m_can/m_can.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index c2b1da87a9ee..1eb6397b79b9 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -1225,6 +1225,17 @@ static void m_can_coalescing_update(struct m_can_classdev *cdev, u32 ir)
 			      HRTIMER_MODE_REL);
 }
 
+static void m_can_tx_peripheral_submit(struct m_can_classdev *cdev)
+{
+	int ffs_idx;
+
+	ffs_idx = ffs(cdev->tx_peripheral_submit);
+	if (ffs_idx > 0) {
+		m_can_write(cdev, M_CAN_TXBAR, ffs_idx - 1);
+		cdev->tx_peripheral_submit &= cdev->tx_peripheral_submit - 1;
+	}
+}
+
 /* This interrupt handler is called either from the interrupt thread or a
  * hrtimer. This has implications like cancelling a timer won't be possible
  * blocking.
@@ -1290,6 +1301,11 @@ static int m_can_interrupt_handler(struct m_can_classdev *cdev)
 			m_can_finish_tx(cdev, 1, frame_len);
 		}
 	} else  {
+		if (cdev->is_peripheral && (ir & IR_TC)) {
+			if (cdev->tx_peripheral_submit > 0)
+				m_can_tx_peripheral_submit(cdev);
+		}
+
 		if (ir & (IR_TEFN | IR_TEFW)) {
 			/* New TX FIFO Element arrived */
 			ret = m_can_echo_tx_event(dev);
@@ -1956,8 +1972,7 @@ static void m_can_tx_submit(struct m_can_classdev *cdev)
 	if (!cdev->is_peripheral)
 		return;
 
-	m_can_write(cdev, M_CAN_TXBAR, cdev->tx_peripheral_submit);
-	cdev->tx_peripheral_submit = 0;
+	m_can_tx_peripheral_submit(cdev);
 }
 
 static void m_can_tx_work_queue(struct work_struct *ws)
-- 
2.34.1

Re: [PATCH] can: m_can: Implement workaround for errata i2278 and i2279

[Marc Kleine-Budde]

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On 14.05.2026 12:25:11, Anurag Dutta wrote:
> Message transmit order is not guaranteed when dedicated TX buffers
> configured with the same Message ID are submitted simultaneously via
> TXBAR write. This is described in J7 errata i2278 and i2279.
>
> As a workaround, introduce m_can_tx_peripheral_submit() to submit
> buffers one at a time using ffs() to find the next pending buffer.
> The TX complete interrupt(IR_TC) triggers submission of the next
> buffer, ensuring strict FIFO ordering.
>
> Link: https://www.ti.com/lit/pdf/sprz530

This errata is for the "J721S2/TDA4VE/TDA4AL/TDA4VL/AM68A Processor
Silicon Revision 1.0". The code path you modify is only active for the
is_peripheral case.

is_peripheral is only set for the tcan4x5x SPI CAN controller, and not
set for memory mapped M_CAN cores as found on the above mentioned TI
processor:

| $ git grep peripheral\ = drivers/net/can/m_can
| drivers/net/can/m_can/m_can_platform.c:149:      mcan_class->is_peripheral = false;
| drivers/net/can/m_can/tcan4x5x-core.c:460:       mcan_class->is_peripheral = true;

The latest Bosch m_can documentation doesn't mention this problem,
neither the TCAN4550 docs. Can this be an integration problem of the SoC
on TI's side?

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
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