[PATCH net-next 0/3] net: stmmac: dwmac-rk: add RK3576 GMAC 25M refout support

[PATCH net-next 0/3] net: stmmac: dwmac-rk: add RK3576 GMAC 25M refout support

[Gavin Gao]

Hi,

Some Rockchip GMAC instances can provide a 25 MHz reference clock output
for an external RGMII PHY. Boards already describe the MAC clock direction
with clock_in_out = "output", but the dwmac-rk driver does not currently
request or enable the corresponding 25 MHz reference output clock.

On RK3576, this means the REFCLKO25M_GMACx_OUT clock may be disabled by
the common clock framework as unused, even though the board expects the
GMAC block to provide the PHY reference clock.

This series adds an optional "clk_mac_25m_refout" clock name to the
Rockchip DWMAC binding, wires it up for RK3576 GMAC0/GMAC1, and enables
it from the dwmac-rk driver when the MAC is configured for RGMII output
clock mode.

The clock remains optional, so existing device trees and SoCs are not
affected.

Tested on a PicoCOM RK3576 ACP board with a Motorcomm YT8521 PHY.
The GMAC 25 MHz reference clock output remains active and Ethernet works.

Gavin Gao (3):
  dt-bindings: net: rockchip-dwmac: Add 25M refout clock
  arm64: dts: rockchip: Add RK3576 GMAC 25M refout clocks
  net: stmmac: dwmac-rk: Enable RGMII 25M refout clock

 .../bindings/net/rockchip-dwmac.yaml          |  1 +
 arch/arm64/boot/dts/rockchip/rk3576.dtsi      |  8 ++---
 .../net/ethernet/stmicro/stmmac/dwmac-rk.c    | 33 ++++++++++++++++++-
 3 files changed, 37 insertions(+), 5 deletions(-)

-- 
2.55.0

[PATCH net-next 1/3] dt-bindings: net: rockchip-dwmac: Add 25M refout clock

[Gavin Gao]

Some Rockchip GMAC instances can provide a 25 MHz reference clock output
for an external RGMII PHY.

Add a clock name for this 25 MHz reference output so SoC dtsi files can
describe it separately from the existing MAC reference clocks.

Signed-off-by: Gavin Gao <attinagaoxu@gmail.com>
---
 Documentation/devicetree/bindings/net/rockchip-dwmac.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
index 0ac7c4b47d6b..074ac274f2e0 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
@@ -81,6 +81,7 @@ properties:
         - pclk_mac
         - clk_mac_ref
         - clk_mac_refout
+        - clk_mac_25m_refout
         - clk_mac_speed
 
   clock_in_out:
-- 
2.55.0

[PATCH net-next 2/3] arm64: dts: rockchip: Add RK3576 GMAC 25M refout clocks

[Gavin Gao]

RK3576 provides REFCLKO25M_GMAC0_OUT and REFCLKO25M_GMAC1_OUT clocks
for the two GMAC instances.

Describe these clocks with the clk_mac_25m_refout clock name so boards
using RGMII output clock mode can let the MAC driver manage the 25 MHz
reference output.

Signed-off-by: Gavin Gao <attinagaoxu@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3576.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 70e67d4dccb8..f1125c2f88ab 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1692,10 +1692,10 @@ gmac0: ethernet@2a220000 {
 			reg = <0x0 0x2a220000 0x0 0x10000>;
 			clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>,
 				 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
-				 <&cru CLK_GMAC0_PTP_REF>;
+				 <&cru CLK_GMAC0_PTP_REF>, <&cru REFCLKO25M_GMAC0_OUT>;
 			clock-names = "stmmaceth", "clk_mac_ref",
 				      "pclk_mac", "aclk_mac",
-				      "ptp_ref";
+				      "ptp_ref", "clk_mac_25m_refout";
 			interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq", "eth_wake_irq";
@@ -1739,10 +1739,10 @@ gmac1: ethernet@2a230000 {
 			reg = <0x0 0x2a230000 0x0 0x10000>;
 			clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>,
 				 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
-				 <&cru CLK_GMAC1_PTP_REF>;
+				 <&cru CLK_GMAC1_PTP_REF>, <&cru REFCLKO25M_GMAC1_OUT>;
 			clock-names = "stmmaceth", "clk_mac_ref",
 				      "pclk_mac", "aclk_mac",
-				      "ptp_ref";
+				      "ptp_ref", "clk_mac_25m_refout";
 			interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq", "eth_wake_irq";
-- 
2.55.0

[PATCH net-next 3/3] net: stmmac: dwmac-rk: Enable RGMII 25M refout clock

[Gavin Gao]

Boards can set clock_in_out = "output" to request a MAC-provided clock,
but dwmac-rk currently does not enable the optional 25 MHz RGMII
reference output clock. The common clock framework may therefore disable
the clock as unused.

Request the optional clk_mac_25m_refout clock in RGMII output mode, set
it to 25 MHz, and keep it enabled while the MAC clocks are enabled.

Signed-off-by: Gavin Gao <attinagaoxu@gmail.com>
---
 .../net/ethernet/stmicro/stmmac/dwmac-rk.c    | 33 ++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 643578266dfc..5e7e5e8f8d62 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -81,6 +81,7 @@ struct rk_priv_data {
 	struct clk_bulk_data *clks;
 	int num_clks;
 	struct clk *clk_phy;
+	struct clk *clk_mac_25m_refout;
 
 	struct reset_control *phy_reset;
 
@@ -1419,6 +1420,24 @@ static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
 		clk_set_rate(bsp_priv->clk_phy, 50000000);
 	}
 
+	if (!bsp_priv->clock_input && phy_interface_mode_is_rgmii(phy_iface)) {
+		bsp_priv->clk_mac_25m_refout =
+			devm_clk_get_optional(dev, "clk_mac_25m_refout");
+		if (IS_ERR(bsp_priv->clk_mac_25m_refout)) {
+			ret = PTR_ERR(bsp_priv->clk_mac_25m_refout);
+			return dev_err_probe(dev, ret,
+					     "Cannot get 25M refout clock\n");
+		}
+
+		if (bsp_priv->clk_mac_25m_refout) {
+			ret = clk_set_rate(bsp_priv->clk_mac_25m_refout,
+					   25000000);
+			if (ret)
+				return dev_err_probe(dev, ret,
+						     "Cannot set 25M refout clock rate\n");
+		}
+	}
+
 	return 0;
 }
 
@@ -1433,9 +1452,13 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 			if (ret)
 				return ret;
 
+			ret = clk_prepare_enable(bsp_priv->clk_mac_25m_refout);
+			if (ret)
+				goto err_disable_clks;
+
 			ret = clk_prepare_enable(bsp_priv->clk_phy);
 			if (ret)
-				return ret;
+				goto err_disable_25m_refout;
 
 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
 				bsp_priv->ops->set_clock_selection(bsp_priv,
@@ -1454,12 +1477,20 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 			clk_bulk_disable_unprepare(bsp_priv->num_clks,
 						   bsp_priv->clks);
 			clk_disable_unprepare(bsp_priv->clk_phy);
+			clk_disable_unprepare(bsp_priv->clk_mac_25m_refout);
 
 			bsp_priv->clk_enabled = false;
 		}
 	}
 
 	return 0;
+
+err_disable_25m_refout:
+	clk_disable_unprepare(bsp_priv->clk_mac_25m_refout);
+err_disable_clks:
+	clk_bulk_disable_unprepare(bsp_priv->num_clks, bsp_priv->clks);
+
+	return ret;
 }
 
 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
-- 
2.55.0

Re: [PATCH net-next 0/3] net: stmmac: dwmac-rk: add RK3576 GMAC 25M refout support

[Maxime Chevallier]

Hi,

On 7/27/26 04:10, Gavin Gao wrote:
> Hi,
> 
> Some Rockchip GMAC instances can provide a 25 MHz reference clock output
> for an external RGMII PHY. Boards already describe the MAC clock direction
> with clock_in_out = "output", but the dwmac-rk driver does not currently
> request or enable the corresponding 25 MHz reference output clock.
> 
> On RK3576, this means the REFCLKO25M_GMACx_OUT clock may be disabled by
> the common clock framework as unused, even though the board expects the
> GMAC block to provide the PHY reference clock.
> 
> This series adds an optional "clk_mac_25m_refout" clock name to the
> Rockchip DWMAC binding, wires it up for RK3576 GMAC0/GMAC1, and enables
> it from the dwmac-rk driver when the MAC is configured for RGMII output
> clock mode.
> 
> The clock remains optional, so existing device trees and SoCs are not
> affected.
> 
> Tested on a PicoCOM RK3576 ACP board with a Motorcomm YT8521 PHY.
> The GMAC 25 MHz reference clock output remains active and Ethernet works.

I have a feeling this is using the common clock framework backwards. The
MAC in this case is a clock provider yet it uses the consumer API.

Shouldn't the MAC instead register a new clock, as a provider, for the ref
out ? The PHY device would then need to get/prepare/enable that clock.

I know we don't have a lot of clock providers in drivers/net/ethernet, but
I think we should have more...

Maxime

Re: [PATCH net-next 0/3] net: stmmac: dwmac-rk: add RK3576 GMAC 25M refout support

[Alexey Charkov]

Hi Maxime,

On Mon, Jul 27, 2026 at 11:11 AM Maxime Chevallier
<maxime.chevallier@bootlin.com> wrote:
>
> Hi,
>
> On 7/27/26 04:10, Gavin Gao wrote:
> > Hi,
> >
> > Some Rockchip GMAC instances can provide a 25 MHz reference clock output
> > for an external RGMII PHY. Boards already describe the MAC clock direction
> > with clock_in_out = "output", but the dwmac-rk driver does not currently
> > request or enable the corresponding 25 MHz reference output clock.
> >
> > On RK3576, this means the REFCLKO25M_GMACx_OUT clock may be disabled by
> > the common clock framework as unused, even though the board expects the
> > GMAC block to provide the PHY reference clock.
> >
> > This series adds an optional "clk_mac_25m_refout" clock name to the
> > Rockchip DWMAC binding, wires it up for RK3576 GMAC0/GMAC1, and enables
> > it from the dwmac-rk driver when the MAC is configured for RGMII output
> > clock mode.
> >
> > The clock remains optional, so existing device trees and SoCs are not
> > affected.
> >
> > Tested on a PicoCOM RK3576 ACP board with a Motorcomm YT8521 PHY.
> > The GMAC 25 MHz reference clock output remains active and Ethernet works.
>
> I have a feeling this is using the common clock framework backwards. The
> MAC in this case is a clock provider yet it uses the consumer API.
>
> Shouldn't the MAC instead register a new clock, as a provider, for the ref
> out ? The PHY device would then need to get/prepare/enable that clock.

The clock name is a misnomer frankly. It's configured in the CRU and
muxed to the output pin via IO registers, so it has little to do with
the GMAC itself - rather it's SoC wide. It's already exposed by the
SoC clock drivers, so nothing to be done in drivers/net/ethernet.

Looks like Motorcomm PHY drivers don't request the clock though, thus
we're seeing a second nearly identical attempt within the same
development cycle to shoehorn clock enablement into the GMAC driver
and binding, where it doesn't belong.

Best regards,
Alexey

Re: [PATCH net-next 0/3] net: stmmac: dwmac-rk: add RK3576 GMAC 25M refout support

[Alexey Charkov]

Hi Gavin,

On Mon, Jul 27, 2026 at 6:10 AM Gavin Gao <attinagaoxu@gmail.com> wrote:
>
> Hi,
>
> Some Rockchip GMAC instances can provide a 25 MHz reference clock output
> for an external RGMII PHY. Boards already describe the MAC clock direction
> with clock_in_out = "output", but the dwmac-rk driver does not currently
> request or enable the corresponding 25 MHz reference output clock.
>
> On RK3576, this means the REFCLKO25M_GMACx_OUT clock may be disabled by
> the common clock framework as unused, even though the board expects the
> GMAC block to provide the PHY reference clock.
>
> This series adds an optional "clk_mac_25m_refout" clock name to the
> Rockchip DWMAC binding, wires it up for RK3576 GMAC0/GMAC1, and enables
> it from the dwmac-rk driver when the MAC is configured for RGMII output
> clock mode.
>
> The clock remains optional, so existing device trees and SoCs are not
> affected.
>
> Tested on a PicoCOM RK3576 ACP board with a Motorcomm YT8521 PHY.
> The GMAC 25 MHz reference clock output remains active and Ethernet works.
>
> Gavin Gao (3):
>   dt-bindings: net: rockchip-dwmac: Add 25M refout clock
>   arm64: dts: rockchip: Add RK3576 GMAC 25M refout clocks
>   net: stmmac: dwmac-rk: Enable RGMII 25M refout clock
>
>  .../bindings/net/rockchip-dwmac.yaml          |  1 +
>  arch/arm64/boot/dts/rockchip/rk3576.dtsi      |  8 ++---
>  .../net/ethernet/stmicro/stmmac/dwmac-rk.c    | 33 ++++++++++++++++++-
>  3 files changed, 37 insertions(+), 5 deletions(-)

Can you please try something like this [1] instead?

[1] https://lore.kernel.org/linux-rockchip/20260719034555.3623003-1-gahing@gahingwoo.com/

The GMAC on RK3576 neither produces nor consumes the clock. CRU is the
producer, and PHY is the consumer. So the GMAC driver shouldn't be the
one to enable it, nor should the dwmac binding have anything to do
with it.

Have a look at how other boards already upstream handle this. For
example, the RK3576 EVB1 uses a similar arrangement but with a
different PHY.

Best regards,
Alexey

Re: [PATCH net-next 0/3] net: stmmac: dwmac-rk: add RK3576 GMAC 25M refout support

[Chaoyi Chen]

On 7/27/2026 3:14 PM, Alexey Charkov wrote:
> Hi Gavin,
> 
> On Mon, Jul 27, 2026 at 6:10 AM Gavin Gao <attinagaoxu@gmail.com> wrote:
>>
>> Hi,
>>
>> Some Rockchip GMAC instances can provide a 25 MHz reference clock output
>> for an external RGMII PHY. Boards already describe the MAC clock direction
>> with clock_in_out = "output", but the dwmac-rk driver does not currently
>> request or enable the corresponding 25 MHz reference output clock.
>>
>> On RK3576, this means the REFCLKO25M_GMACx_OUT clock may be disabled by
>> the common clock framework as unused, even though the board expects the
>> GMAC block to provide the PHY reference clock.
>>
>> This series adds an optional "clk_mac_25m_refout" clock name to the
>> Rockchip DWMAC binding, wires it up for RK3576 GMAC0/GMAC1, and enables
>> it from the dwmac-rk driver when the MAC is configured for RGMII output
>> clock mode.
>>
>> The clock remains optional, so existing device trees and SoCs are not
>> affected.
>>
>> Tested on a PicoCOM RK3576 ACP board with a Motorcomm YT8521 PHY.
>> The GMAC 25 MHz reference clock output remains active and Ethernet works.
>>
>> Gavin Gao (3):
>>   dt-bindings: net: rockchip-dwmac: Add 25M refout clock
>>   arm64: dts: rockchip: Add RK3576 GMAC 25M refout clocks
>>   net: stmmac: dwmac-rk: Enable RGMII 25M refout clock
>>
>>  .../bindings/net/rockchip-dwmac.yaml          |  1 +
>>  arch/arm64/boot/dts/rockchip/rk3576.dtsi      |  8 ++---
>>  .../net/ethernet/stmicro/stmmac/dwmac-rk.c    | 33 ++++++++++++++++++-
>>  3 files changed, 37 insertions(+), 5 deletions(-)
> 
> Can you please try something like this [1] instead?
> 
> [1] https://lore.kernel.org/linux-rockchip/20260719034555.3623003-1-gahing@gahingwoo.com/
> 
> The GMAC on RK3576 neither produces nor consumes the clock. CRU is the
> producer, and PHY is the consumer. So the GMAC driver shouldn't be the
> one to enable it, nor should the dwmac binding have anything to do
> with it.
> 
> Have a look at how other boards already upstream handle this. For
> example, the RK3576 EVB1 uses a similar arrangement but with a
> different PHY.

Yep, we had a similar fix, but it was rejected. Please see how RK3576 EVB1 does it:

https://lore.kernel.org/all/20250910-rk3576-evb-network-v1-1-68ed4df272a2@collabora.com/


-- 
Best, 
Chaoyi

Re: [PATCH net-next 0/3] net: stmmac: dwmac-rk: add RK3576 GMAC 25M refout support

[Jiaxing Hu]

Hi Gavin,

We ran into the same thing on the ArmSoM CM5-IO. As Alexey and Maxime
say, the 25 MHz output is a CRU clock muxed to a pin, so the PHY should
enable it, not the GMAC. I sent that for the YT8531:

  https://lore.kernel.org/all/20260719034555.3623003-1-gahing@gahingwoo.com/

It has Andrew's Reviewed-by and is waiting for net-next. On the CM5-IO
the YT8531 comes up at 1000 Mbit/s with no dwmac-rk change and no dwmac
binding change.

Your board has a YT8521, which uses yt8521_probe(), so it needs the same
devm_clk_get_optional_enabled() there rather than in yt8531_probe(). I am
happy to fold YT8521 into my patch, or you can send a small follow-up
once mine lands, whichever the maintainers prefer. The board DTS then
just needs a clocks phandle to the CRU on the PHY node.

Thanks,
Jiaxing