Re: [net-next,PATCH v2] enetc: Increase eMDIO MDC rate to 2.5 MHz

[Vladimir Oltean <vladimir.oltean@nxp.com>]

On Wed, Sep 30, 2026 at 06:19:04AM +0200, Marek Vasut wrote:
> Are those clock which feed MDC clock available via clock framework on LS ?
> If so, we could calculate the divider based on those clock.

Yes.

On LS1028A, the ENETC clock selection is made by a mux called HWA_CGA_M4_CLK_SEL
(Hardware Accelerator Block Cluster Group A Mux 4 Clock Select).

You can describe that in ls1028a.dtsi like this (note that in the RM,
the mux numbering is one-based, while in the device tree it is 0-based,
so 3 is actually "MUX 4"):

 			enetc_mdio_pf3: mdio@0,3 {
 				compatible = "pci1957,ee01", "fsl,enetc-mdio";
 				reg = <0x000300 0 0 0 0>;
+				clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 			};

Upon clk_get_rate(), the qoriq clockgen driver will use the device tree
definition to index the hwaccel[] array and find the ls1028a_hwa4 structure.
This defines what values the HWA4CSR register can legally take, and what
each means. It will read HWA4CSR[HWACLKSEL] as 0011 (meaning Cluster PLL2
divide-by-3). Then to calculate this clock rate, it knows it must read
CGA_PLL2 and to divide by PLL_DIV3 (1200 / 3 = 400 MHz).

Note the ENETC PTP device already has this property defined (which is
OK, all ENETC devices share the same clock).

Without a 'clocks' and/or 'clock-frequency' property, we have to figure
out a default that works for everyone, or if that fails.

For example, with 400 MHz enet_clk on LS1028A, the original
MDIO_CFG_CLKDIV value of 258 used to produce an MDC frequency of
400000000÷((258×2)+1)=773 KHz.

Your new MDIO_CFG_CLKDIV value of 66 produces 400000000÷((66)+1)=3 MHz,
which is too high to be a default value. So from LS perspective, this
patch needs to be reverted.

Generally it is assumed that low MDIO clock frequencies are not a
problem. Otherwise, drivers/net/mdio/mdio-bitbang.c could never work.
It seems TJA1120 is the odd one for requiring a maximum MDC clock
period of 1000 ns.

Please use xgmac_mdio_set_mdc_freq() as model, since it exists to
solve a very similar issue as you are trying to do.