From: Dan Williams <dan.j.williams@intel.com>
To: <alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
<pabeni@redhat.com>, <edumazet@google.com>,
<dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v16 04/22] cxl: Move register/capability check to driver
Date: Wed, 21 May 2025 11:23:35 -0700 [thread overview]
Message-ID: <682e1a27e285e_1626e100c9@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250514132743.523469-5-alejandro.lucero-palau@amd.com>
alejandro.lucero-palau@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
>
> Type3 has some mandatory capabilities which are optional for Type2.
>
> In order to support same register/capability discovery code for both
> types, avoid any assumption about what capabilities should be there, and
> export the capabilities found for the caller doing the capabilities
> check based on the expected ones.
>
> Add a function for facilitating the report of capabilities missing the
> expected ones.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/pci.c | 41 +++++++++++++++++++++++++++++++++++++++--
> drivers/cxl/core/port.c | 8 ++++----
> drivers/cxl/core/regs.c | 38 ++++++++++++++++++++++----------------
> drivers/cxl/cxl.h | 6 +++---
> drivers/cxl/cxlpci.h | 2 +-
> drivers/cxl/pci.c | 24 +++++++++++++++++++++---
> include/cxl/cxl.h | 24 ++++++++++++++++++++++++
> 7 files changed, 114 insertions(+), 29 deletions(-)
[..]
>
> @@ -434,7 +449,7 @@ static void cxl_unmap_regblock(struct cxl_register_map *map)
> map->base = NULL;
> }
>
> -static int cxl_probe_regs(struct cxl_register_map *map)
> +static int cxl_probe_regs(struct cxl_register_map *map, unsigned long *caps)
> {
> struct cxl_component_reg_map *comp_map;
> struct cxl_device_reg_map *dev_map;
> @@ -444,21 +459,12 @@ static int cxl_probe_regs(struct cxl_register_map *map)
> switch (map->reg_type) {
> case CXL_REGLOC_RBI_COMPONENT:
> comp_map = &map->component_map;
> - cxl_probe_component_regs(host, base, comp_map);
> + cxl_probe_component_regs(host, base, comp_map, caps);
> dev_dbg(host, "Set up component registers\n");
> break;
> case CXL_REGLOC_RBI_MEMDEV:
> dev_map = &map->device_map;
> - cxl_probe_device_regs(host, base, dev_map);
> - if (!dev_map->status.valid || !dev_map->mbox.valid ||
> - !dev_map->memdev.valid) {
> - dev_err(host, "registers not found: %s%s%s\n",
> - !dev_map->status.valid ? "status " : "",
> - !dev_map->mbox.valid ? "mbox " : "",
> - !dev_map->memdev.valid ? "memdev " : "");
> - return -ENXIO;
> - }
> -
> + cxl_probe_device_regs(host, base, dev_map, caps);
I thought we talked about this before [1] , i.e. that there is no need
to pass @caps through the stack.
[1]: http://lore.kernel.org/678b06a26cddc_20fa29492@dwillia2-xfh.jf.intel.com.notmuch
Here is the proposal that moves this simple check to the leaf consumer
where it belongs vs plumbing @caps everywhere, note how this removes
burden from the core, not add burden to support more use cases:
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index ecdb22ae6952..5f511cf4bab0 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -434,7 +434,7 @@ static void cxl_unmap_regblock(struct cxl_register_map *map)
map->base = NULL;
}
-static int cxl_probe_regs(struct cxl_register_map *map)
+static void cxl_probe_regs(struct cxl_register_map *map)
{
struct cxl_component_reg_map *comp_map;
struct cxl_device_reg_map *dev_map;
@@ -450,22 +450,11 @@ static int cxl_probe_regs(struct cxl_register_map *map)
case CXL_REGLOC_RBI_MEMDEV:
dev_map = &map->device_map;
cxl_probe_device_regs(host, base, dev_map);
- if (!dev_map->status.valid || !dev_map->mbox.valid ||
- !dev_map->memdev.valid) {
- dev_err(host, "registers not found: %s%s%s\n",
- !dev_map->status.valid ? "status " : "",
- !dev_map->mbox.valid ? "mbox " : "",
- !dev_map->memdev.valid ? "memdev " : "");
- return -ENXIO;
- }
-
dev_dbg(host, "Probing device registers...\n");
break;
default:
break;
}
-
- return 0;
}
int cxl_setup_regs(struct cxl_register_map *map)
@@ -476,10 +465,10 @@ int cxl_setup_regs(struct cxl_register_map *map)
if (rc)
return rc;
- rc = cxl_probe_regs(map);
+ cxl_probe_regs(map);
cxl_unmap_regblock(map);
- return rc;
+ return 0;
}
EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, "CXL");
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index d5447c7d540f..cfe4b5fa948a 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -945,6 +945,16 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
+ /* Check for mandatory CXL Memory Class Device capabilities */
+ if (!map.device_map.status.valid || !map.device_map.mbox.valid ||
+ !map.device_map.memdev.valid) {
+ dev_err(&pdev->dev, "registers not found: %s%s%s\n",
+ !map.device_map.status.valid ? "status " : "",
+ !map.device_map.mbox.valid ? "mbox " : "",
+ !map.device_map.memdev.valid ? "memdev " : "");
+ return -ENXIO;
+ }
+
rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs);
if (rc)
return rc;
next prev parent reply other threads:[~2025-05-21 18:23 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 13:27 [PATCH v16 00/22] Type2 device basic support alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-05-20 2:43 ` Alison Schofield
2025-05-20 7:18 ` Alejandro Lucero Palau
2025-05-20 20:06 ` Dave Jiang
2025-05-21 9:30 ` Alejandro Lucero Palau
2025-05-20 7:17 ` dan.j.williams
2025-05-21 10:44 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-20 7:37 ` dan.j.williams
2025-05-21 10:50 ` Alejandro Lucero Palau
2025-05-21 17:12 ` Dan Williams
2025-05-22 8:49 ` Alejandro Lucero Palau
2025-05-22 19:41 ` Dan Williams
2025-06-04 8:09 ` Jonathan Cameron
2025-05-14 13:27 ` [PATCH v16 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-05-20 2:42 ` Alison Schofield
2025-05-21 17:44 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 04/22] cxl: Move register/capability check to driver alejandro.lucero-palau
2025-05-20 2:41 ` Alison Schofield
2025-05-21 18:23 ` Dan Williams [this message]
2025-05-22 9:45 ` Alejandro Lucero Palau
2025-05-22 19:51 ` Dan Williams
2025-05-23 9:12 ` Alejandro Lucero Palau
2025-05-23 16:55 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 05/22] cxl: Add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-20 2:41 ` Alison Schofield
2025-05-21 18:28 ` Dan Williams
2025-05-22 9:52 ` Alejandro Lucero Palau
2025-05-22 20:04 ` Dan Williams
2025-06-06 11:59 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-05-21 18:34 ` Dan Williams
2025-05-22 10:07 ` Alejandro Lucero Palau
2025-05-22 20:22 ` Dan Williams
2025-05-22 20:53 ` Dan Williams
2025-05-22 21:09 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 07/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-05-20 2:40 ` Alison Schofield
2025-05-21 18:47 ` Dan Williams
2025-05-22 10:24 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-05-20 2:40 ` Alison Schofield
2025-05-21 18:49 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-05-20 2:36 ` Alison Schofield
2025-05-21 19:31 ` Dan Williams
2025-05-22 10:56 ` Alejandro Lucero Palau
2025-05-22 20:31 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-05-21 19:56 ` Dan Williams
2025-06-06 12:59 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-20 2:39 ` Alison Schofield
2025-05-21 20:23 ` Dan Williams
2025-06-06 13:09 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-05-21 20:28 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-05-20 2:39 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-05-20 2:37 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-05-20 2:38 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-05-20 2:37 ` Alison Schofield
2025-05-21 20:45 ` Dan Williams
2025-06-06 13:27 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 19/22] cxl: Add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-20 2:36 ` Alison Schofield
2025-05-21 20:49 ` Dan Williams
2025-06-06 13:39 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 20/22] sfc: create cxl region alejandro.lucero-palau
2025-05-21 21:01 ` Dan Williams
2025-06-06 13:44 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-05-20 2:35 ` Alison Schofield
2025-05-21 21:31 ` Dan Williams
2025-06-06 14:03 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-21 21:48 ` Dan Williams
2025-05-23 1:13 ` Edward Cree
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