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From: Dan Williams <dan.j.williams@intel.com>
To: Alejandro Lucero Palau <alucerop@amd.com>,
	Dan Williams <dan.j.williams@intel.com>,
	<alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
	<netdev@vger.kernel.org>, <edward.cree@amd.com>,
	<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
	<edumazet@google.com>, <dave.jiang@intel.com>
Cc: Ben Cheatham <benjamin.cheatham@amd.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v16 05/22] cxl: Add function for type2 cxl regs setup
Date: Thu, 22 May 2025 13:04:47 -0700	[thread overview]
Message-ID: <682f835fba701_3e70100a5@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <d64fad40-20f9-44ff-867a-8caacd70767b@amd.com>

Alejandro Lucero Palau wrote:
[..]
> > The driver should know in advance if calling:
> >
> >      cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
> >
> > ...will fail. Put that logic where it belongs in the probe function of
> > the type-2 driver directly. This helper is not helping, it is just
> > obfuscating.
> 
> 
> As I said in the previous email, I disagree. The CXL API should be 
> handling all this. A client only cares about certain things, let's say 
> manageable things like capabilities, without going deep into CXL specs 
> about how all that needs to be implemented. This patch introduces a 
> function embedding different calls for those innerworkings which should 
> only be handled by the CXL core.

No. Please keep this policy out of the core. Do not invent a new
"capabilities" contract that the CXL core needs to maintain, and do not
add thin "cxl_pci_accel_" helpers that just wrap existing core
functionality. Call existing core functions directly and only augment
them at the point where fundamental assumptions are violated between
the "Type-3" and "Type-2" device models.

If the fundamental assumption violation boils down to a policy
difference between Type-2 and Type-3 then move that policy out of the
core. For example, register discovery is a mechanism, what the client
does with the result of that mechanism is policy and belongs in the
leaf/client. It was an accident of implementation that mandatory Type-3
register blocks were validated in the core not in cxl_pci from the
outset.

  reply	other threads:[~2025-05-22 20:05 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-14 13:27 [PATCH v16 00/22] Type2 device basic support alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-05-20  2:43   ` Alison Schofield
2025-05-20  7:18     ` Alejandro Lucero Palau
2025-05-20 20:06       ` Dave Jiang
2025-05-21  9:30         ` Alejandro Lucero Palau
2025-05-20  7:17   ` dan.j.williams
2025-05-21 10:44     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-20  7:37   ` dan.j.williams
2025-05-21 10:50     ` Alejandro Lucero Palau
2025-05-21 17:12       ` Dan Williams
2025-05-22  8:49         ` Alejandro Lucero Palau
2025-05-22 19:41           ` Dan Williams
2025-06-04  8:09             ` Jonathan Cameron
2025-05-14 13:27 ` [PATCH v16 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-05-20  2:42   ` Alison Schofield
2025-05-21 17:44   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 04/22] cxl: Move register/capability check to driver alejandro.lucero-palau
2025-05-20  2:41   ` Alison Schofield
2025-05-21 18:23   ` Dan Williams
2025-05-22  9:45     ` Alejandro Lucero Palau
2025-05-22 19:51       ` Dan Williams
2025-05-23  9:12         ` Alejandro Lucero Palau
2025-05-23 16:55           ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 05/22] cxl: Add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-20  2:41   ` Alison Schofield
2025-05-21 18:28   ` Dan Williams
2025-05-22  9:52     ` Alejandro Lucero Palau
2025-05-22 20:04       ` Dan Williams [this message]
2025-06-06 11:59         ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-05-21 18:34   ` Dan Williams
2025-05-22 10:07     ` Alejandro Lucero Palau
2025-05-22 20:22       ` Dan Williams
2025-05-22 20:53         ` Dan Williams
2025-05-22 21:09           ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 07/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-05-20  2:40   ` Alison Schofield
2025-05-21 18:47   ` Dan Williams
2025-05-22 10:24     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-05-20  2:40   ` Alison Schofield
2025-05-21 18:49   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-05-20  2:36   ` Alison Schofield
2025-05-21 19:31   ` Dan Williams
2025-05-22 10:56     ` Alejandro Lucero Palau
2025-05-22 20:31       ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-05-21 19:56   ` Dan Williams
2025-06-06 12:59     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-20  2:39   ` Alison Schofield
2025-05-21 20:23   ` Dan Williams
2025-06-06 13:09     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-05-21 20:28   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-05-20  2:39   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-05-20  2:37   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-05-20  2:38   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-05-20  2:37   ` Alison Schofield
2025-05-21 20:45   ` Dan Williams
2025-06-06 13:27     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 19/22] cxl: Add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-20  2:36   ` Alison Schofield
2025-05-21 20:49   ` Dan Williams
2025-06-06 13:39     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 20/22] sfc: create cxl region alejandro.lucero-palau
2025-05-21 21:01   ` Dan Williams
2025-06-06 13:44     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-05-20  2:35   ` Alison Schofield
2025-05-21 21:31   ` Dan Williams
2025-06-06 14:03     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-21 21:48   ` Dan Williams
2025-05-23  1:13     ` Edward Cree

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