From: Dan Williams <dan.j.williams@intel.com>
To: Dan Williams <dan.j.williams@intel.com>,
Alejandro Lucero Palau <alucerop@amd.com>,
<alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
<netdev@vger.kernel.org>, <edward.cree@amd.com>,
<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>, <dave.jiang@intel.com>
Cc: Martin Habets <habetsm.xilinx@gmail.com>,
Zhi Wang <zhi@nvidia.com>, Edward Cree <ecree.xilinx@gmail.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Ben Cheatham <benjamin.cheatham@amd.com>
Subject: Re: [PATCH v16 06/22] sfc: make regs setup with checking and set media ready
Date: Thu, 22 May 2025 13:53:05 -0700 [thread overview]
Message-ID: <682f8eb15905c_3e70100b5@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <682f8797ac1b_3e7010017@dwillia2-xfh.jf.intel.com.notmuch>
Dan Williams wrote:
> Alejandro Lucero Palau wrote:
> >
> > On 5/21/25 19:34, Dan Williams wrote:
> > > alejandro.lucero-palau@ wrote:
> > >> From: Alejandro Lucero <alucerop@amd.com>
> > >>
> > >> Use cxl code for registers discovery and mapping.
> > >>
> > >> Validate capabilities found based on those registers against expected
> > >> capabilities.
> > >>
> > >> Set media ready explicitly as there is no means for doing so without
> > >> a mailbox and without the related cxl register, not mandatory for type2.
> > >>
> > >> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> > >> Reviewed-by: Martin Habets <habetsm.xilinx@gmail.com>
> > >> Reviewed-by: Zhi Wang <zhi@nvidia.com>
> > >> Acked-by: Edward Cree <ecree.xilinx@gmail.com>
> > >> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > >> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
> > >> ---
> > >> drivers/net/ethernet/sfc/efx_cxl.c | 26 ++++++++++++++++++++++++++
> > >> 1 file changed, 26 insertions(+)
> > >>
> > >> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
> > >> index 753d5b7d49b6..e94af8bf3a79 100644
> > >> --- a/drivers/net/ethernet/sfc/efx_cxl.c
> > >> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
> > >> @@ -19,10 +19,13 @@
> > >>
> > >> int efx_cxl_init(struct efx_probe_data *probe_data)
> > >> {
> > >> + DECLARE_BITMAP(expected, CXL_MAX_CAPS) = {};
> > >> + DECLARE_BITMAP(found, CXL_MAX_CAPS) = {};
> > >> struct efx_nic *efx = &probe_data->efx;
> > >> struct pci_dev *pci_dev = efx->pci_dev;
> > >> struct efx_cxl *cxl;
> > >> u16 dvsec;
> > >> + int rc;
> > >>
> > >> probe_data->cxl_pio_initialised = false;
> > >>
> > >> @@ -43,6 +46,29 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
> > >> if (!cxl)
> > >> return -ENOMEM;
> > >>
> > >> + set_bit(CXL_DEV_CAP_HDM, expected);
> > >> + set_bit(CXL_DEV_CAP_RAS, expected);
> > >> +
> > >> + rc = cxl_pci_accel_setup_regs(pci_dev, &cxl->cxlds, found);
> > >> + if (rc) {
> > >> + pci_err(pci_dev, "CXL accel setup regs failed");
> > >> + return rc;
> > >> + }
> > >> +
> > >> + /*
> > >> + * Checking mandatory caps are there as, at least, a subset of those
> > >> + * found.
> > >> + */
> > >> + if (cxl_check_caps(pci_dev, expected, found))
> > >> + return -ENXIO;
> > > This all looks like an obfuscated way of writing:
> > >
> > > cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
> > > if (!map.component_map.ras.valid || !map.component_map.hdm_decoder.valid)
> > > /* sfc cxl expectations not met */
Now, I do notice that the proposal above got the registers blocks wrong.
I.e. that should be:
cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
if (!map.component_map.ras.valid || !map.component_map.hdm_decoder.valid)
/* sfc cxl expectations not met */
I also apologize for the negative connotation of "obfuscated". I should
have said:
"This simply boils down to the following..." which is yes, a bit of a
mouthful to type out, but it has the benefit of no new changes to the
core which is my preference until it becomes exceedingly clear that new
APIs are needed.
So,
map.component_map.hdm_decoder.valid
map.component_map.ras.valid
...instead of:
set_bit(CXL_DEV_CAP_HDM, expected);
set_bit(CXL_DEV_CAP_RAS, expected);
...please.
next prev parent reply other threads:[~2025-05-22 20:53 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 13:27 [PATCH v16 00/22] Type2 device basic support alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-05-20 2:43 ` Alison Schofield
2025-05-20 7:18 ` Alejandro Lucero Palau
2025-05-20 20:06 ` Dave Jiang
2025-05-21 9:30 ` Alejandro Lucero Palau
2025-05-20 7:17 ` dan.j.williams
2025-05-21 10:44 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-20 7:37 ` dan.j.williams
2025-05-21 10:50 ` Alejandro Lucero Palau
2025-05-21 17:12 ` Dan Williams
2025-05-22 8:49 ` Alejandro Lucero Palau
2025-05-22 19:41 ` Dan Williams
2025-06-04 8:09 ` Jonathan Cameron
2025-05-14 13:27 ` [PATCH v16 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-05-20 2:42 ` Alison Schofield
2025-05-21 17:44 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 04/22] cxl: Move register/capability check to driver alejandro.lucero-palau
2025-05-20 2:41 ` Alison Schofield
2025-05-21 18:23 ` Dan Williams
2025-05-22 9:45 ` Alejandro Lucero Palau
2025-05-22 19:51 ` Dan Williams
2025-05-23 9:12 ` Alejandro Lucero Palau
2025-05-23 16:55 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 05/22] cxl: Add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-20 2:41 ` Alison Schofield
2025-05-21 18:28 ` Dan Williams
2025-05-22 9:52 ` Alejandro Lucero Palau
2025-05-22 20:04 ` Dan Williams
2025-06-06 11:59 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-05-21 18:34 ` Dan Williams
2025-05-22 10:07 ` Alejandro Lucero Palau
2025-05-22 20:22 ` Dan Williams
2025-05-22 20:53 ` Dan Williams [this message]
2025-05-22 21:09 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 07/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-05-20 2:40 ` Alison Schofield
2025-05-21 18:47 ` Dan Williams
2025-05-22 10:24 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-05-20 2:40 ` Alison Schofield
2025-05-21 18:49 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-05-20 2:36 ` Alison Schofield
2025-05-21 19:31 ` Dan Williams
2025-05-22 10:56 ` Alejandro Lucero Palau
2025-05-22 20:31 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-05-21 19:56 ` Dan Williams
2025-06-06 12:59 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-20 2:39 ` Alison Schofield
2025-05-21 20:23 ` Dan Williams
2025-06-06 13:09 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-05-21 20:28 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-05-20 2:39 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-05-20 2:37 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-05-20 2:38 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-05-20 2:37 ` Alison Schofield
2025-05-21 20:45 ` Dan Williams
2025-06-06 13:27 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 19/22] cxl: Add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-20 2:36 ` Alison Schofield
2025-05-21 20:49 ` Dan Williams
2025-06-06 13:39 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 20/22] sfc: create cxl region alejandro.lucero-palau
2025-05-21 21:01 ` Dan Williams
2025-06-06 13:44 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-05-20 2:35 ` Alison Schofield
2025-05-21 21:31 ` Dan Williams
2025-06-06 14:03 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-21 21:48 ` Dan Williams
2025-05-23 1:13 ` Edward Cree
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=682f8eb15905c_3e70100b5@dwillia2-xfh.jf.intel.com.notmuch \
--to=dan.j.williams@intel.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=alejandro.lucero-palau@amd.com \
--cc=alucerop@amd.com \
--cc=benjamin.cheatham@amd.com \
--cc=dave.jiang@intel.com \
--cc=davem@davemloft.net \
--cc=ecree.xilinx@gmail.com \
--cc=edumazet@google.com \
--cc=edward.cree@amd.com \
--cc=habetsm.xilinx@gmail.com \
--cc=kuba@kernel.org \
--cc=linux-cxl@vger.kernel.org \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=zhi@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox