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From: Dan Williams <dan.j.williams@intel.com>
To: <alejandro.lucero-palau@amd.com>, <linux-cxl@vger.kernel.org>,
	<netdev@vger.kernel.org>, <dan.j.williams@intel.com>,
	<edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>,
	<pabeni@redhat.com>, <edumazet@google.com>,
	<dave.jiang@intel.com>
Cc: Alejandro Lucero <alucerop@amd.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v16 18/22] cxl: Allow region creation by type2 drivers
Date: Wed, 21 May 2025 13:45:48 -0700	[thread overview]
Message-ID: <682e3b7cf2b2_1626e100ce@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20250514132743.523469-19-alejandro.lucero-palau@amd.com>

alejandro.lucero-palau@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 
> Creating a CXL region requires userspace intervention through the cxl
> sysfs files. Type2 support should allow accelerator drivers to create
> such cxl region from kernel code.
> 
> Adding that functionality and integrating it with current support for
> memory expanders.
> 
> Based on https://lore.kernel.org/linux-cxl/168592159835.1948938.1647215579839222774.stgit@dwillia2-xfh.jf.intel.com/
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  drivers/cxl/core/region.c | 140 +++++++++++++++++++++++++++++++++++---
>  drivers/cxl/port.c        |   5 +-
>  include/cxl/cxl.h         |   4 ++
>  3 files changed, 140 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 4113ee6daec9..f82da914d125 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -2316,6 +2316,21 @@ static int cxl_region_detach(struct cxl_endpoint_decoder *cxled)
>  	return rc;
>  }
>  
> +/**
> + * cxl_accel_region_detach -  detach a region from a Type2 device
> + *
> + * @cxled: Type2 endpoint decoder to detach the region from.
> + *
> + * Returns 0 or error.
> + */
> +int cxl_accel_region_detach(struct cxl_endpoint_decoder *cxled)
> +{
> +	guard(rwsem_write)(&cxl_region_rwsem);
> +	cxled->part = -1;
> +	return cxl_region_detach(cxled);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_accel_region_detach, "CXL");

There's nothing "accel" about the above sequence, it is nearly identical
to cxl_decoder_kill_region().

In general there does not need to be a parallel universe of "cxl_accel_"
helpers for Type-2, just use existing infrastructure and maybe enlighten
it a bit to accommodate a Type-2 nuance.

> +
>  void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled)
>  {
>  	down_write(&cxl_region_rwsem);
> @@ -2822,6 +2837,14 @@ cxl_find_region_by_name(struct cxl_root_decoder *cxlrd, const char *name)
>  	return to_cxl_region(region_dev);
>  }
>  
> +static void drop_region(struct cxl_region *cxlr)
> +{
> +	struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
> +	struct cxl_port *port = cxlrd_to_port(cxlrd);
> +
> +	devm_release_action(port->uport_dev, unregister_region, cxlr);
> +}
> +
>  static ssize_t delete_region_store(struct device *dev,
>  				   struct device_attribute *attr,
>  				   const char *buf, size_t len)
> @@ -3526,14 +3549,12 @@ static int __construct_region(struct cxl_region *cxlr,
>  	return 0;
>  }
>  
> -/* Establish an empty region covering the given HPA range */
> -static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> -					   struct cxl_endpoint_decoder *cxled)
> +static struct cxl_region *construct_region_begin(struct cxl_root_decoder *cxlrd,
> +						 struct cxl_endpoint_decoder *cxled)
>  {
>  	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> -	struct cxl_port *port = cxlrd_to_port(cxlrd);
>  	struct cxl_dev_state *cxlds = cxlmd->cxlds;
> -	int rc, part = READ_ONCE(cxled->part);
> +	int part = READ_ONCE(cxled->part);
>  	struct cxl_region *cxlr;
>  
>  	do {
> @@ -3542,13 +3563,23 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>  				       cxled->cxld.target_type);
>  	} while (IS_ERR(cxlr) && PTR_ERR(cxlr) == -EBUSY);
>  
> -	if (IS_ERR(cxlr)) {
> +	if (IS_ERR(cxlr))
>  		dev_err(cxlmd->dev.parent,
>  			"%s:%s: %s failed assign region: %ld\n",
>  			dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev),
>  			__func__, PTR_ERR(cxlr));
> -		return cxlr;
> -	}
> +	return cxlr;
> +};
> +
> +/* Establish an empty region covering the given HPA range */
> +static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> +					   struct cxl_endpoint_decoder *cxled)
> +{
> +	struct cxl_port *port = cxlrd_to_port(cxlrd);
> +	struct cxl_region *cxlr;
> +	int rc;
> +
> +	cxlr = construct_region_begin(cxlrd, cxled);
>  
>  	rc = __construct_region(cxlr, cxlrd, cxled);
>  	if (rc) {
> @@ -3559,6 +3590,99 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>  	return cxlr;
>  }
>  
> +static struct cxl_region *
> +__construct_new_region(struct cxl_root_decoder *cxlrd,
> +		       struct cxl_endpoint_decoder *cxled, int ways)

What is the point of an @ways argument when @cxled is not an array? It
was an array in the original proposal. Recall that this interface needs
to be useful not only to Type-2 but also the nascent CXL PMEM case which
will likely need to create interleave CXL PMEM regions from label data.

  parent reply	other threads:[~2025-05-21 20:46 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-14 13:27 [PATCH v16 00/22] Type2 device basic support alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-05-20  2:43   ` Alison Schofield
2025-05-20  7:18     ` Alejandro Lucero Palau
2025-05-20 20:06       ` Dave Jiang
2025-05-21  9:30         ` Alejandro Lucero Palau
2025-05-20  7:17   ` dan.j.williams
2025-05-21 10:44     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-20  7:37   ` dan.j.williams
2025-05-21 10:50     ` Alejandro Lucero Palau
2025-05-21 17:12       ` Dan Williams
2025-05-22  8:49         ` Alejandro Lucero Palau
2025-05-22 19:41           ` Dan Williams
2025-06-04  8:09             ` Jonathan Cameron
2025-05-14 13:27 ` [PATCH v16 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-05-20  2:42   ` Alison Schofield
2025-05-21 17:44   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 04/22] cxl: Move register/capability check to driver alejandro.lucero-palau
2025-05-20  2:41   ` Alison Schofield
2025-05-21 18:23   ` Dan Williams
2025-05-22  9:45     ` Alejandro Lucero Palau
2025-05-22 19:51       ` Dan Williams
2025-05-23  9:12         ` Alejandro Lucero Palau
2025-05-23 16:55           ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 05/22] cxl: Add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-20  2:41   ` Alison Schofield
2025-05-21 18:28   ` Dan Williams
2025-05-22  9:52     ` Alejandro Lucero Palau
2025-05-22 20:04       ` Dan Williams
2025-06-06 11:59         ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-05-21 18:34   ` Dan Williams
2025-05-22 10:07     ` Alejandro Lucero Palau
2025-05-22 20:22       ` Dan Williams
2025-05-22 20:53         ` Dan Williams
2025-05-22 21:09           ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 07/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-05-20  2:40   ` Alison Schofield
2025-05-21 18:47   ` Dan Williams
2025-05-22 10:24     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-05-20  2:40   ` Alison Schofield
2025-05-21 18:49   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-05-20  2:36   ` Alison Schofield
2025-05-21 19:31   ` Dan Williams
2025-05-22 10:56     ` Alejandro Lucero Palau
2025-05-22 20:31       ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-05-21 19:56   ` Dan Williams
2025-06-06 12:59     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-20  2:39   ` Alison Schofield
2025-05-21 20:23   ` Dan Williams
2025-06-06 13:09     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-05-21 20:28   ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-05-20  2:39   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-05-20  2:37   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-05-20  2:38   ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-05-20  2:37   ` Alison Schofield
2025-05-21 20:45   ` Dan Williams [this message]
2025-06-06 13:27     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 19/22] cxl: Add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-20  2:36   ` Alison Schofield
2025-05-21 20:49   ` Dan Williams
2025-06-06 13:39     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 20/22] sfc: create cxl region alejandro.lucero-palau
2025-05-21 21:01   ` Dan Williams
2025-06-06 13:44     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-05-20  2:35   ` Alison Schofield
2025-05-21 21:31   ` Dan Williams
2025-06-06 14:03     ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-21 21:48   ` Dan Williams
2025-05-23  1:13     ` Edward Cree

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