From: Andrew Lunn <andrew@lunn.ch>
To: Gustav Ekelund <gustaek@axis.com>
Cc: "Marek Behún" <marek.behun@nic.cz>,
"Gustav Ekelund" <gustav.ekelund@axis.com>,
"Florian Fainelli" <f.fainelli@gmail.com>,
"Vladimir Oltean" <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
kernel@axis.com, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH net] net: dsa: mv88e6xxx: Reset mv88e6393x watchdog register
Date: Tue, 28 Mar 2023 15:45:51 +0200 [thread overview]
Message-ID: <be2b5084-9cab-4cc7-ba50-a53dd71dfea5@lunn.ch> (raw)
In-Reply-To: <c92234f1-099b-29a0-f093-c54c046d304a@axis.com>
On Tue, Mar 28, 2023 at 03:34:03PM +0200, Gustav Ekelund wrote:
> 1) Marvell has confirmed that 6393x (Amethyst) differs from 6390 (Peridot)
> with quote: “I tried this on my board and see G2 offset 0x1B index 12 bit 0
> does not clear, I also tried doing a SWReset and the bit is still 1. I did
> try the same on a Peridot board and it clears as advertised.”
>
> 2) Marvell are not aware of any other stuck bits, but has confirmed that the
> WD event bits are not cleared on SW reset which is indeed contradictory to
> what the data sheet suggests.
Hi Gustav
Please expand the commit message with a summary of this
information. It answers the questions both Marek and i have been
asking, so deserves to be in the commit message.
Andrew
next prev parent reply other threads:[~2023-03-28 13:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-28 11:55 [PATCH net] net: dsa: mv88e6xxx: Reset mv88e6393x watchdog register Gustav Ekelund
2023-03-28 12:06 ` Marek Behún
2023-03-28 12:30 ` Andrew Lunn
2023-03-28 12:47 ` Marek Behún
2023-03-28 13:34 ` Gustav Ekelund
2023-03-28 13:45 ` Andrew Lunn [this message]
2023-03-28 14:47 ` Marek Behún
2023-03-30 13:29 ` Gustav Ekelund
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