Re: [PATCH net] net: dsa: mv88e6xxx: Reset mv88e6393x watchdog register

[Andrew Lunn <andrew@lunn.ch>]

> > +static int mv88e6393x_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
> > +{
> > +	mv88e6390_watchdog_action(chip, irq);
> > +
> > +	mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
> > +			   MV88E6390_G2_WDOG_CTL_UPDATE |
> > +			   MV88E6390_G2_WDOG_CTL_PTR_EVENT);
> > +
> > +	return IRQ_HANDLED;
> > +}
> 
> Shouldn't this update be in .irq_setup() method? In the commit message
> you're saying that the problem is that bits aren't cleared with SW
> reset. So I would guess that the change should be in the setup of
> watchdog IRQ, not in IRQ action?

I think it is a bit more complex than that. At least for the 6352,
which i just looked at the data sheet, the interrupt bits are listed
as "ROC". Which is missing from the list of definitions, but seems to
mean Read Only, Clear on read. So even if it was not cleared on
software reset, it would only fire once, and then be cleared.

The problem description here is that it does not clear on read, it
needs an explicit write. Which suggests Marvell changed it for the
6393.

So i have a couple of questions:

1) Is this new behaviour limited to the 6393, or does the 6390 also
need this write?

2) What about other interrupts? Is this the only one which has changed
behaviour?

	Andrew