Re: [PATCH net] net: dsa: mv88e6xxx: Reset mv88e6393x watchdog register

[Gustav Ekelund <gustaek@axis.com>]

On 3/28/23 14:47, Marek Behún wrote:
> On Tue, Mar 28, 2023 at 02:30:37PM +0200, Andrew Lunn wrote:
>>>> +static int mv88e6393x_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
>>>> +{
>>>> +	mv88e6390_watchdog_action(chip, irq);
>>>> +
>>>> +	mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
>>>> +			   MV88E6390_G2_WDOG_CTL_UPDATE |
>>>> +			   MV88E6390_G2_WDOG_CTL_PTR_EVENT);
>>>> +
>>>> +	return IRQ_HANDLED;
>>>> +}
>>>
>>> Shouldn't this update be in .irq_setup() method? In the commit message
>>> you're saying that the problem is that bits aren't cleared with SW
>>> reset. So I would guess that the change should be in the setup of
>>> watchdog IRQ, not in IRQ action?
>>
>> I think it is a bit more complex than that. At least for the 6352,
>> which i just looked at the data sheet, the interrupt bits are listed
>> as "ROC". Which is missing from the list of definitions, but seems to
>> mean Read Only, Clear on read. So even if it was not cleared on
>> software reset, it would only fire once, and then be cleared.
>>
>> The problem description here is that it does not clear on read, it
>> needs an explicit write. Which suggests Marvell changed it for the
>> 6393.
>>
>> So i have a couple of questions:
>>
>> 1) Is this new behaviour limited to the 6393, or does the 6390 also
>> need this write?
> 
> OK I am looking at the func specs of 6390 and 6393x, at the table
> descrinbing the Data Path Watch Dog Event register (index 0x12 of global
> 2, which is the one being written), and the tables are exactly the same.
> 
> For every non-reserved bit there is the following:
>    This bit is cleared by a SWReset (Global 1 offset 0x04). It will
>    automatically be cleared to zero if the SWReset on WD bit (index 0x13)
>    is set to a one and this event's Func bit is cleared to zero (index
>    0x11).
> 
> Moreover only bit 0 of this register (ForceWD Event) is RWR. Bits 1 to 3
> (EgressWD Event, QC WD Event and CT WD Event) are all RO. Bits 4-7 are
> reserved. (Once again, exactly as in func spec of 6390.)
> 
> So I am not exactly sure what is going on. The errata document I have
> does not mention watch dog at all.
> 
> Marek
> 
>> 2) What about other interrupts? Is this the only one which has changed
>> behaviour?
>>
>> 	Andrew
1) Marvell has confirmed that 6393x (Amethyst) differs from 6390 
(Peridot) with quote: “I tried this on my board and see G2 offset 0x1B 
index 12 bit 0 does not clear, I also tried doing a SWReset and the bit 
is still 1. I did try the same on a Peridot board and it clears as 
advertised.”

2) Marvell are not aware of any other stuck bits, but has confirmed that 
the WD event bits are not cleared on SW reset which is indeed 
contradictory to what the data sheet suggests.

Bug can be reproduced on 6393x with the Force WD event by writing 0x9201 
to G2 offset 0x1b.

Best regards
Gustav