Re: [PATCH 11/27] gpu: nova-core: regs: add msgq v2 BAR0 register declarations

[Zhi Wang <zhiw@nvidia.com>]

On Tue, 18 Aug 2026 20:52:04 -0700
John Hubbard <jhubbard@nvidia.com> wrote:

Looking good to me.

Reviewed-by: Zhi Wang <zhiw@nvidia.com>

Z.

> Msgq v2 moves the four ring pointers out of the in-memory headers and
> into BAR0. NV_PGSP_QUEUE_HEAD already exists as the v0 doorbell, so
> add NV_PGSP_QUEUE_TAIL, NV_PGSP_MSGQ_HEAD, and NV_PGSP_MSGQ_TAIL at
> the queue-0 offsets.
> 
> Nova only uses queue 0, so the registers are scalars rather than
> 8-element arrays. A comment records the full hardware layout for
> future multi-queue work.
> 
> Assisted-by: Cursor:claude-opus-5
> Signed-off-by: John Hubbard <jhubbard@nvidia.com>
> ---
>  drivers/gpu/nova-core/gsp/regs.rs | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/nova-core/gsp/regs.rs
> b/drivers/gpu/nova-core/gsp/regs.rs index 9a48aa87e7fb..d2e40ed13123
> 100644 --- a/drivers/gpu/nova-core/gsp/regs.rs
> +++ b/drivers/gpu/nova-core/gsp/regs.rs
> @@ -5,6 +5,18 @@
>  use crate::regs::NV_PBUS_SW_SCRATCH;
>  
>  // PGSP
> +//
> +// The msgq v2 wire protocol replaces the in-memory ring pointers
> with four +// BAR0 registers per queue:
> +//
> +//     NV_PGSP_QUEUE_HEAD[i] @ 0x00110c00 + i*8  (CPU TX write,
> doorbell) +//     NV_PGSP_QUEUE_TAIL[i] @ 0x00110c04 + i*8  (GSP TX
> read) +//     NV_PGSP_MSGQ_HEAD[i]  @ 0x00110c80 + i*8  (GSP RX write)
> +//     NV_PGSP_MSGQ_TAIL[i]  @ 0x00110c84 + i*8  (CPU RX read)
> +//
> +// Nova only uses queue 0, so the four registers are declared as
> single +// scalars at the i=0 offsets. NV_PGSP_QUEUE_HEAD is also
> used as the v0 +// doorbell, which is why it predates the others.
>  
>  register! {
>      pub(super) NV_PGSP_QUEUE_HEAD(u32) @ 0x00110c00 {
> @@ -12,6 +24,24 @@
>      }
>  }
>  
> +register! {
> +    pub(super) NV_PGSP_QUEUE_TAIL(u32) @ 0x00110c04 {
> +        31:0    address;
> +    }
> +}
> +
> +register! {
> +    pub(super) NV_PGSP_MSGQ_HEAD(u32) @ 0x00110c80 {
> +        31:0    address;
> +    }
> +}
> +
> +register! {
> +    pub(super) NV_PGSP_MSGQ_TAIL(u32) @ 0x00110c84 {
> +        31:0    address;
> +    }
> +}
> +
>  // PBUS
>  
>  register! {