[PATCH v2] gpu: nova-core: clarify FSP ordering in the chipset table

[PATCH v2] gpu: nova-core: clarify FSP ordering in the chipset table

[John Hubbard]

The Chipset enum lists GPUs in chip-ID order, but FSP capability does
not follow that order. Hopper and Blackwell boot the GSP via FSP, while
Ada, whose chip IDs fall numerically between Hopper and Blackwell, uses
the older SEC2 booter path instead. Add a comment so the table ordering
does not suggest that everything past Hopper uses FSP.

Suggested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
---

Changes since v1 [1]:

* Keep the existing "Hopper and later" wording in uses_fsp() rather than
  changing it, and put the clarification entirely in the chipset table
  comment (Timur Tabi).

* Reword that comment to describe the Hopper/Ada chip-ID inversion and to
  say "Hopper and later" excludes Ada and means Hopper, Blackwell, Rubin,
  and everything after that, so it stays correct once Rubin is added
  (Timur Tabi).

[1] https://lore.kernel.org/all/20260610234128.547952-1-jhubbard@nvidia.com/


 drivers/gpu/nova-core/gpu.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index b3c91731db45..20b59bb6b7d9 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -91,6 +91,10 @@ fn try_from(value: u32) -> Result<Self, Self::Error> {
     GA104 = 0x174,
     GA106 = 0x176,
     GA107 = 0x177,
+    // Chip IDs are in numerical order, which does not match FSP capability. Hopper (GH100) has a
+    // lower chip ID than Ada (AD10x), yet Hopper boots the GSP via FSP while Ada uses the older
+    // SEC2 booter. We therefore consider Hopper to be after Ada, so "Hopper and later" excludes
+    // Ada and means Hopper, Blackwell, Rubin, and everything after that.
     // Hopper
     GH100 = 0x180,
     // Ada

base-commit: 550dc7536644db2d67c6f8cf525bba682fba08d9
-- 
2.54.0

Re: [PATCH v2] gpu: nova-core: clarify FSP ordering in the chipset table

[Gary Guo]

On Fri Jun 12, 2026 at 5:04 AM BST, John Hubbard wrote:
> The Chipset enum lists GPUs in chip-ID order, but FSP capability does
> not follow that order. Hopper and Blackwell boot the GSP via FSP, while
> Ada, whose chip IDs fall numerically between Hopper and Blackwell, uses
> the older SEC2 booter path instead. Add a comment so the table ordering
> does not suggest that everything past Hopper uses FSP.
>
> Suggested-by: Timur Tabi <ttabi@nvidia.com>
> Signed-off-by: John Hubbard <jhubbard@nvidia.com>
> ---
>
> Changes since v1 [1]:
>
> * Keep the existing "Hopper and later" wording in uses_fsp() rather than
>   changing it, and put the clarification entirely in the chipset table
>   comment (Timur Tabi).
>
> * Reword that comment to describe the Hopper/Ada chip-ID inversion and to
>   say "Hopper and later" excludes Ada and means Hopper, Blackwell, Rubin,
>   and everything after that, so it stays correct once Rubin is added
>   (Timur Tabi).
>
> [1] https://lore.kernel.org/all/20260610234128.547952-1-jhubbard@nvidia.com/
>
>
>  drivers/gpu/nova-core/gpu.rs | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
> index b3c91731db45..20b59bb6b7d9 100644
> --- a/drivers/gpu/nova-core/gpu.rs
> +++ b/drivers/gpu/nova-core/gpu.rs
> @@ -91,6 +91,10 @@ fn try_from(value: u32) -> Result<Self, Self::Error> {
>      GA104 = 0x174,
>      GA106 = 0x176,
>      GA107 = 0x177,
> +    // Chip IDs are in numerical order, which does not match FSP capability. Hopper (GH100) has a
> +    // lower chip ID than Ada (AD10x), yet Hopper boots the GSP via FSP while Ada uses the older
> +    // SEC2 booter. We therefore consider Hopper to be after Ada, so "Hopper and later" excludes
> +    // Ada and means Hopper, Blackwell, Rubin, and everything after that.

This would be inconsistent with the derived `PartialOrd` implementation?

If we consider Hopper to be after Ada, then we should be able to `assert!(GH100 > AD102);`

Best,
Gary

>      // Hopper
>      GH100 = 0x180,
>      // Ada
>
> base-commit: 550dc7536644db2d67c6f8cf525bba682fba08d9

Re: [PATCH v2] gpu: nova-core: clarify FSP ordering in the chipset table

[Timur Tabi]

On Fri, 2026-06-12 at 13:06 +0100, Gary Guo wrote:
> This would be inconsistent with the derived `PartialOrd` implementation?
> 
> If we consider Hopper to be after Ada, then we should be able to `assert!(GH100 > AD102);`

This is a comment about how we describe things, not how the code works.  It's because we
frequently say "Hopper or later" to describe our GPUs' capabilities.  

Re: [PATCH v2] gpu: nova-core: clarify FSP ordering in the chipset table

[Gary Guo]

On Fri Jun 12, 2026 at 4:43 PM BST, Timur Tabi wrote:
> On Fri, 2026-06-12 at 13:06 +0100, Gary Guo wrote:
>> This would be inconsistent with the derived `PartialOrd` implementation?
>> 
>> If we consider Hopper to be after Ada, then we should be able to `assert!(GH100 > AD102);`
>
> This is a comment about how we describe things, not how the code works.  It's because we
> frequently say "Hopper or later" to describe our GPUs' capabilities.  

If the code often needs to say "Hopper or later", then I'd say the comparison
would want to be consistent with that too, no?

When would you want `GH100 < AD102` in your code?

Best,
Gary

Re: [PATCH v2] gpu: nova-core: clarify FSP ordering in the chipset table

[Timur Tabi]

On Fri, 2026-06-12 at 17:07 +0100, Gary Guo wrote:
> If the code often needs to say "Hopper or later", then I'd say the comparison
> would want to be consistent with that too, no?
> 
> When would you want `GH100 < AD102` in your code?

I guess I'm just not being clear.  The phrase "Hopper and later" is just a phrase to describe
Hopper, Blackwell, Rubin, and whatever comes after it.  The whole point behind the comment is
that you're supposed to ignore the chip_id numbering when you read that phrase.

Re: [PATCH v2] gpu: nova-core: clarify FSP ordering in the chipset table

[John Hubbard]

On 6/12/26 9:24 AM, Timur Tabi wrote:
> On Fri, 2026-06-12 at 17:07 +0100, Gary Guo wrote:
>> If the code often needs to say "Hopper or later", then I'd say the comparison
>> would want to be consistent with that too, no?
>>
>> When would you want `GH100 < AD102` in your code?
> 
> I guess I'm just not being clear.  The phrase "Hopper and later" is just a phrase to describe
> Hopper, Blackwell, Rubin, and whatever comes after it.  The whole point behind the comment is
> that you're supposed to ignore the chip_id numbering when you read that phrase.

And clearly the comment has failed in its goal, seeing as how our
first reader had trouble understanding what we meant. :)  Gary,
any thoughts about how to clarify this? Or is this whole idea
of talking about Hopper and later turning into a problem...?

thanks,
-- 
John Hubbard

Re: [PATCH v2] gpu: nova-core: clarify FSP ordering in the chipset table

[Timur Tabi]

On Fri, 2026-06-12 at 10:17 -0700, John Hubbard wrote:
> And clearly the comment has failed in its goal, seeing as how our
> first reader had trouble understanding what we meant. :)  Gary,
> any thoughts about how to clarify this? Or is this whole idea
> of talking about Hopper and later turning into a problem...?

I mean, it can't be a problem because that's how everyone in Nvidia talks.  The point of the
comment is to reconcile the language we use with the hardware register.

We're not going to stop saying "Hopper and later", and we're never going to mean that to include
Ada.  

We probably need to comment the Architecture enum too:

    pub(crate) enum Architecture with TryFrom<Bounded<u32, 6>> {
        Turing = 0x16,
        Ampere = 0x17,
        Hopper = 0x18,
        Ada = 0x19,
        BlackwellGB10x = 0x1a,
        BlackwellGB20x = 0x1b,
    }

Ugh.  Maybe we should swap Hopper and Ada here?