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From: Mark Hatle <mark.hatle@kernel.crashing.org>
To: openembedded-core@lists.openembedded.org
Subject: [PATCH v2 6/7] kernel.bbclass: State riscv required tune_features for Linux
Date: Tue, 17 Jun 2025 18:39:43 -0500	[thread overview]
Message-ID: <1750203584-32065-7-git-send-email-mark.hatle@kernel.crashing.org> (raw)
In-Reply-To: <1750203584-32065-1-git-send-email-mark.hatle@kernel.crashing.org>

From: Mark Hatle <mark.hatle@amd.com>

Required:
   rv32ima_zicsr_zifencei
   rv64ima_zicsr_zifencei

See the arch/riscv/Makefile:

riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei

Signed-off-by: Mark Hatle <mark.hatle@amd.com>
---
 meta/classes-recipe/kernel.bbclass | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/meta/classes-recipe/kernel.bbclass b/meta/classes-recipe/kernel.bbclass
index 2d9943c8a0..eb03424dfc 100644
--- a/meta/classes-recipe/kernel.bbclass
+++ b/meta/classes-recipe/kernel.bbclass
@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: MIT
 #
 
-inherit linux-kernel-base kernel-module-split
+inherit linux-kernel-base kernel-module-split features_check
 
 COMPATIBLE_HOST = ".*-linux"
 
+# Linux has a minimum ISA requires on riscv, see arch/riscv/Makefile
+REQUIRED_TUNE_FEATURES:riscv32 = "rv 32 i m a zicsr zifencei"
+REQUIRED_TUNE_FEATURES:riscv64 = "rv 64 i m a zicsr zifencei"
+
 KERNEL_PACKAGE_NAME ??= "kernel"
 KERNEL_DEPLOYSUBDIR ??= "${@ "" if (d.getVar("KERNEL_PACKAGE_NAME") == "kernel") else d.getVar("KERNEL_PACKAGE_NAME") }"
 
-- 
2.34.1



  parent reply	other threads:[~2025-06-17 23:39 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-17 23:39 [PATCH v2 0/7] ISA based RISC-V tune implementation Mark Hatle
2025-06-17 23:39 ` [PATCH v2 1/7] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle
2025-06-18  4:00   ` [OE-core] " Alistair Francis
2025-06-18 14:12     ` Mark Hatle
     [not found]     ` <184A2891E949D242.11882@lists.openembedded.org>
2025-06-18 16:50       ` Mark Hatle
2025-06-17 23:39 ` [PATCH v2 2/7] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections ** DO NOT MERGE ** Mark Hatle
2025-06-17 23:39 ` [PATCH v2 3/7] u-boot: Dynamic RISC-V ISA configuration Mark Hatle
2025-06-17 23:39 ` [PATCH v2 4/7] qemuriscv: Dynamically configure qemu CPU Mark Hatle
2025-06-17 23:39 ` [PATCH v2 5/7] features_check.bbclass: Add support for required TUNE_FEATURES Mark Hatle
2025-06-17 23:39 ` Mark Hatle [this message]
2025-06-17 23:39 ` [PATCH v2 7/7] rust-target-config.bbclass: Update for new riscv TUNE_FEATURES Mark Hatle
2026-01-14 10:16   ` [OE-core] " Alexander Kanavin
2026-01-14 10:33     ` Richard Purdie
2026-01-14 10:50       ` Alexander Kanavin
2026-01-14 10:57         ` Richard Purdie
2025-06-18 19:29 ` [OE-core] [PATCH v2 0/7] ISA based RISC-V tune implementation Gyorgy Sarvari

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