From: Richard Purdie <richard.purdie@linuxfoundation.org>
To: Alexander Kanavin <alex.kanavin@gmail.com>,
mark.hatle@kernel.crashing.org
Cc: openembedded-core@lists.openembedded.org, Paul Barker <paul@pbarker.dev>
Subject: Re: [OE-core] [PATCH v2 7/7] rust-target-config.bbclass: Update for new riscv TUNE_FEATURES
Date: Wed, 14 Jan 2026 10:33:14 +0000 [thread overview]
Message-ID: <4ba4ca643eb20de0eddbcb4895598d22831b12be.camel@linuxfoundation.org> (raw)
In-Reply-To: <CANNYZj-7dDr=UwCzDHW-EqMRPWvsSKX3DABLoAtQx1D0ba8k7g@mail.gmail.com>
On Wed, 2026-01-14 at 11:16 +0100, Alexander Kanavin wrote:
> On Wed, 18 Jun 2025 at 01:39, Mark Hatle via lists.openembedded.org
> <mark.hatle=kernel.crashing.org@lists.openembedded.org> wrote:
> > - tspec['llvm-abiname'] = "lp64d"
> > + tspec['llvm-abiname'] = d.getVar('TUNE_RISCV_ABI')
> > if "riscv32" in tspec['llvm-target']:
> > - tspec['llvm-abiname'] = "ilp32d"
> > + tspec['llvm-abiname'] = d.getVar('TUNE_RISCV_ABI')
>
> Unfortunately this adds a dependency on TUNE_RISCV_ABI (which is set
> only if the target is a risc-v machine) to rust-native's
> rust_gen_targets task, breaking sstate reuse for it between risc-v and
> any other target. I can imagine other native pieces written in rust
> will have the same issue.
>
> It's not immediately obvious to me how to address this, so I'd really
> appreciate suggestions. The code is hairy.
>
> Ticket: https://bugzilla.yoctoproject.org/show_bug.cgi?id=16132
Nice find. I worry about our sstate tests not covering this. We might need to do:
-rust_gen_target[vardepsexclude] += "ABIEXTENSION llvm_cpu"
+rust_gen_target[vardepsexclude] += "ABIEXTENSION llvm_cpu TUNE_RISCV_ABI"
Cheers,
Richard
next prev parent reply other threads:[~2026-01-14 10:33 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-17 23:39 [PATCH v2 0/7] ISA based RISC-V tune implementation Mark Hatle
2025-06-17 23:39 ` [PATCH v2 1/7] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle
2025-06-18 4:00 ` [OE-core] " Alistair Francis
2025-06-18 14:12 ` Mark Hatle
[not found] ` <184A2891E949D242.11882@lists.openembedded.org>
2025-06-18 16:50 ` Mark Hatle
2025-06-17 23:39 ` [PATCH v2 2/7] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections ** DO NOT MERGE ** Mark Hatle
2025-06-17 23:39 ` [PATCH v2 3/7] u-boot: Dynamic RISC-V ISA configuration Mark Hatle
2025-06-17 23:39 ` [PATCH v2 4/7] qemuriscv: Dynamically configure qemu CPU Mark Hatle
2025-06-17 23:39 ` [PATCH v2 5/7] features_check.bbclass: Add support for required TUNE_FEATURES Mark Hatle
2025-06-17 23:39 ` [PATCH v2 6/7] kernel.bbclass: State riscv required tune_features for Linux Mark Hatle
2025-06-17 23:39 ` [PATCH v2 7/7] rust-target-config.bbclass: Update for new riscv TUNE_FEATURES Mark Hatle
2026-01-14 10:16 ` [OE-core] " Alexander Kanavin
2026-01-14 10:33 ` Richard Purdie [this message]
2026-01-14 10:50 ` Alexander Kanavin
2026-01-14 10:57 ` Richard Purdie
2025-06-18 19:29 ` [OE-core] [PATCH v2 0/7] ISA based RISC-V tune implementation Gyorgy Sarvari
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