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From: Richard Purdie <richard.purdie@linuxfoundation.org>
To: Alexander Kanavin <alex.kanavin@gmail.com>
Cc: mark.hatle@kernel.crashing.org,
	openembedded-core@lists.openembedded.org,
	 Paul Barker <paul@pbarker.dev>
Subject: Re: [OE-core] [PATCH v2 7/7] rust-target-config.bbclass: Update for new riscv TUNE_FEATURES
Date: Wed, 14 Jan 2026 10:57:33 +0000	[thread overview]
Message-ID: <e52b1b42d9b9d2d9d2c5d051ebbd266dd01885ac.camel@linuxfoundation.org> (raw)
In-Reply-To: <CANNYZj8VxKnzaq67qmXEziy8k+iMn-n8AGBQgC8rt48P8b35ew@mail.gmail.com>

On Wed, 2026-01-14 at 11:50 +0100, Alexander Kanavin wrote:
> On Wed, 14 Jan 2026 at 11:33, Richard Purdie
> <richard.purdie@linuxfoundation.org> wrote:
> 
> > Nice find. I worry about our sstate tests not covering this. We
> > might need to do:
> > 
> > -rust_gen_target[vardepsexclude] += "ABIEXTENSION llvm_cpu"
> > +rust_gen_target[vardepsexclude] += "ABIEXTENSION llvm_cpu
> > TUNE_RISCV_ABI"
> 
> I thought of that, but would this rebuild correctly if someone first
> builds for one TUNE_RISCV_ABI, then for another? I just don't know
> enough about it to run experiments. It probably would, as that
> variable feeds into TUNE_CCARGS.

The comment above this line says:

# These are accounted for in tmpdir path names so don't need to be in the task sig

so in theory this would handle changes to different machines with
different ABIs fine, as long as those ABIs have different tmpdir paths
which they should.

It doesn't guard against the value of TUNE_RISCV_ABI changing for a
given target as that wouldn't rebuild correctly.

I guess if we wanted to be really clear, we could probably do something
like:

RUSTCONFIG_EXCLUDEVARS = ""
RUSTCONFIG_EXCLUDEVARS:class-native = "ABIEXTENSION llvm_cpu TUNE_RISCV_ABI"
RUSTCONFIG_EXCLUDEVARS:class-nativesdk = "ABIEXTENSION llvm_cpu TUNE_RISCV_ABI"
rust_gen_target[vardepsexclude] += "${RUSTCONFIG_EXCLUDEVARS}"

but I guess we've not thought that was worth the effort in the past...

Cheers,

Richard


  reply	other threads:[~2026-01-14 10:57 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-17 23:39 [PATCH v2 0/7] ISA based RISC-V tune implementation Mark Hatle
2025-06-17 23:39 ` [PATCH v2 1/7] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle
2025-06-18  4:00   ` [OE-core] " Alistair Francis
2025-06-18 14:12     ` Mark Hatle
     [not found]     ` <184A2891E949D242.11882@lists.openembedded.org>
2025-06-18 16:50       ` Mark Hatle
2025-06-17 23:39 ` [PATCH v2 2/7] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections ** DO NOT MERGE ** Mark Hatle
2025-06-17 23:39 ` [PATCH v2 3/7] u-boot: Dynamic RISC-V ISA configuration Mark Hatle
2025-06-17 23:39 ` [PATCH v2 4/7] qemuriscv: Dynamically configure qemu CPU Mark Hatle
2025-06-17 23:39 ` [PATCH v2 5/7] features_check.bbclass: Add support for required TUNE_FEATURES Mark Hatle
2025-06-17 23:39 ` [PATCH v2 6/7] kernel.bbclass: State riscv required tune_features for Linux Mark Hatle
2025-06-17 23:39 ` [PATCH v2 7/7] rust-target-config.bbclass: Update for new riscv TUNE_FEATURES Mark Hatle
2026-01-14 10:16   ` [OE-core] " Alexander Kanavin
2026-01-14 10:33     ` Richard Purdie
2026-01-14 10:50       ` Alexander Kanavin
2026-01-14 10:57         ` Richard Purdie [this message]
2025-06-18 19:29 ` [OE-core] [PATCH v2 0/7] ISA based RISC-V tune implementation Gyorgy Sarvari

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