From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser
Date: Fri, 18 May 2018 04:41:17 +0000 [thread overview]
Message-ID: <1526618477.10055.7.camel@intel.com> (raw)
In-Reply-To: <9678d4f9-911e-86c0-748c-0672e780459d@denx.de>
On Thu, 2018-05-17 at 11:38 +0200, Marek Vasut wrote:
> On 05/17/2018 10:44 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2018-05-17 at 10:24 +0200, Marek Vasut wrote:
> > >
> > > On 05/17/2018 06:38 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Sat, 2018-05-12 at 22:30 +0200, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > The A10 clock manager parsed DT bindings generated by Quartus
> > > > > the
> > > > > bsp-editor to configure the A10 clocks. Sadly, those DT
> > > > > bindings
> > > > > changed at some point. The clock manager patch used the old
> > > > > ones,
> > > > > this patch replaces the bindings parser with one for the new
> > > > > set.
> > > > >
> > > > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > > ---
> > > > > arch/arm/mach-socfpga/clock_manager_arria10.c | 158
> > > > > ++++++++++++++-------
> > > > > .../include/mach/clock_manager_arria10.h | 2 +-
> > > > > 2 files changed, 111 insertions(+), 49 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > index 4ee6a82b5f..defa2f6261 100644
> > > > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > > @@ -9,6 +9,9 @@
> > > > > #include <dm.h>
> > > > > #include <asm/arch/clock_manager.h>
> > > > >
> > > > > +static const struct socfpga_clock_manager
> > > > > *clock_manager_base =
> > > > > + (struct socfpga_clock_manager
> > > > > *)SOCFPGA_CLKMGR_ADDRESS;
> > > > > +
> > > > > static u32 eosc1_hz;
> > > > > static u32 cb_intosc_hz;
> > > > > static u32 f2s_free_hz;
> > > > > @@ -64,89 +67,150 @@ struct perpll_cfg {
> > > > > u32 cntr8clk_cnt;
> > > > > u32 cntr8clk_src;
> > > > > u32 cntr9clk_cnt;
> > > > > + u32 cntr9clk_src;
> > > > Why add this? I believe this is not exist.
> > > It exists in the altera sources and it matches the pattern. What
> > > do
> > > you
> > > mean by "this is not exist" ?
> > >
> > we don't have cntr9clk_src in perpll.
> https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v201
> 4.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/clock_manager
> .c#L229
>
That is the bug, and i have already fixed it in mainstream
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-socfpga/clock_m
anager_arria10.c;h=4ee6a82b5f75215d6930d488aa39c572d1610073;hb=HEAD#l11
4
> You do ...
>
next prev parent reply other threads:[~2018-05-18 4:41 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile Marek Vasut
2018-05-16 10:13 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 03/12] ARM: socfpga: Synchronize Arria10 DTs Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 04/12] ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 05/12] ARM: socfpga: Repair A10 EMAC reset handling Marek Vasut
2018-05-16 10:24 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 06/12] ARM: socfpga: Rename the gen5 sdram driver to more specific name Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 07/12] ARM: socfpga: Add DRAM bank size initialization function Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 08/12] ARM: socfpga: Add DDR driver for Arria 10 Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 09/12] configs: Add DDR Kconfig support " Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 10/12] ARM: socfpga: Enable SPL memory allocation Marek Vasut
2018-05-16 10:26 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 11/12] ARM: socfpga: Adding clock frequency info for U-Boot Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 12/12] ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot Marek Vasut
2018-05-17 4:38 ` [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Chee, Tien Fong
2018-05-17 8:24 ` Marek Vasut
2018-05-17 8:44 ` Chee, Tien Fong
2018-05-17 9:38 ` Marek Vasut
2018-05-18 4:41 ` Chee, Tien Fong [this message]
2018-05-18 7:50 ` Marek Vasut
2018-05-18 8:39 ` Chee, Tien Fong
2018-05-18 8:42 ` Marek Vasut
2018-05-18 8:53 ` Chee, Tien Fong
2018-05-18 8:58 ` Marek Vasut
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