From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 09/12] configs: Add DDR Kconfig support for Arria 10
Date: Sat, 12 May 2018 22:30:17 +0200 [thread overview]
Message-ID: <20180512203020.17422-9-marex@denx.de> (raw)
In-Reply-To: <20180512203020.17422-1-marex@denx.de>
From: Tien Fong Chee <tien.fong.chee@intel.com>
This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/mach-socfpga/Kconfig | 1 +
drivers/ddr/altera/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 824c9fc2ba..b8fc81b20c 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -10,6 +10,7 @@ config TARGET_SOCFPGA_ARRIA5
config TARGET_SOCFPGA_ARRIA10
bool
select SPL_BOARD_INIT if SPL
+ select ALTERA_SDRAM
config TARGET_SOCFPGA_CYCLONE5
bool
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 021ec1d857..2b28a97f6e 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,5 +1,5 @@
config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
- depends on TARGET_SOCFPGA_GEN5
+ depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
help
Enable DDR SDRAM controller for the SoCFPGA devices.
--
2.16.2
next prev parent reply other threads:[~2018-05-12 20:30 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile Marek Vasut
2018-05-16 10:13 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 03/12] ARM: socfpga: Synchronize Arria10 DTs Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 04/12] ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 05/12] ARM: socfpga: Repair A10 EMAC reset handling Marek Vasut
2018-05-16 10:24 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 06/12] ARM: socfpga: Rename the gen5 sdram driver to more specific name Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 07/12] ARM: socfpga: Add DRAM bank size initialization function Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 08/12] ARM: socfpga: Add DDR driver for Arria 10 Marek Vasut
2018-05-12 20:30 ` Marek Vasut [this message]
2018-05-12 20:30 ` [U-Boot] [PATCH 10/12] ARM: socfpga: Enable SPL memory allocation Marek Vasut
2018-05-16 10:26 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 11/12] ARM: socfpga: Adding clock frequency info for U-Boot Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 12/12] ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot Marek Vasut
2018-05-17 4:38 ` [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Chee, Tien Fong
2018-05-17 8:24 ` Marek Vasut
2018-05-17 8:44 ` Chee, Tien Fong
2018-05-17 9:38 ` Marek Vasut
2018-05-18 4:41 ` Chee, Tien Fong
2018-05-18 7:50 ` Marek Vasut
2018-05-18 8:39 ` Chee, Tien Fong
2018-05-18 8:42 ` Marek Vasut
2018-05-18 8:53 ` Chee, Tien Fong
2018-05-18 8:58 ` Marek Vasut
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